摘要
随着半导体制造工艺的发展,异构多核片上系统可以集成多个具有不同功能的处理器核,并充分利用各处理器核的性能优势对多种特定类型的任务进行加速,能够同时满足嵌入式应用在芯片面积、计算性能、功耗等多方面的需求,因而被广泛应用于嵌入式计算领域。然而,随着嵌入式应用的日益普及和芯片集成度的不断提高,异构多核片上系统的设计面临着越来越严峻的挑战,其中包括：1)如何提高系统硬件平台的灵活性,以适应经常变化的嵌入式应用需求；2)如何提高系统中处理器核的应用效率,以充分利用系统的性能潜力；3)如何为异构多核片上系统建立形式化模型,特别是准确刻画其复杂的动态行为特征,以帮助设计人员对系统软/硬件设计的正确性和性能进行验证和评估。
本文针对上述问题分别展开研究,所做的主要工作及创新特色包括：
1)通过在系统软/硬件设计流程、模块通信接口与并行编程模型等方面提供对动态部分重构特性的支持,将动态部分重构技术与面向服务的异构多核(SOMP)体系结构结合在一起,以提高系统的灵活性。本文在基于现场可编程门阵列(FPGA)的开发板上实现了具有动态部分重构特性的SOMP原型系统,从而验证了本文提出的设计方法的正确性。此外,为了证明动态部分重构特性的有效性,本文还通过实验对原型系统的重构开销和动态部分重构特性引入的资源开销等进行了评估。
2)本文对Amdahl定律进行了扩展,将Amdahl定律应用于异构多核片上系统。根据扩展,我们对处理器核配置、可并行化任务的比重、任务划分策略等因素对系统性能的影响进行了量化分析,并从理论上指出了为获得系统最高性能应满足的条件。该扩展对优化异构多核片上系统设计并提高系统应用效率具有指导意义。
3)充分发掘应用的任务级并行度是提高多核系统应用效率的有效方法之一。为此,本文对异构多核片上系统的自动化任务并行方法进行了研究。通过将多核任务视为抽象指令,我们首次将指令级的记分牌算法扩展到异构多核片上系统,提出了任务级记分牌调度方法。该调度方法能动态地检测任务间的依赖关系并自动将任务分配到不同的处理器核上并行执行,以提高应用的任务级并行度。我们在SOMP原型系统上实现了任务级记分牌调度方法,并通过实验将它与其它先进的动态调度方法进行了对比。对比实验的结果证明了任务级记分牌调度算法具有较低的运行时调度开销。
4)本文使用形式化语言——有色Petri网对异构多核片上系统进行了建模。与以往的研究工作不同的是,本文提出的有色Petri网模型不仅可以描述系统的处理器核、存储单元和任务等静态元素,还能够对系统运行过程中的任务依赖性检测、任务分配等动态行为进行刻画,因而可用于对系统的任务执行过程及相应的调度算法进行建模。借助于该模型,设计人员可以尽早对异构多核片上系统的软/硬件设计进行性能评估。本文使用该模型对SOMP原型系统及其任务乱序执行过程进行了仿真。我们通过对比和分析模型仿真结果与原型系统的实际运行情况,证明了本文提出的有色Petri网模型可以准确地仿真异构多核片上系统的执行过程。
The development of semiconductor manufacturing technology allows a heterogeneous Multi-Processor System-on-Chip (MPSoC) integrating multiple processor cores of various functionalities in it. Thus, heterogeneous MPSoCs can make full advantage of each core to accelerate multiple specified categories of tasks, and thereby simultaneously satisfies the requirements of embedded applications on many aspects, such as chip area, computing performance and power consumption. For the reason above, heterogeneous MPSoCs are widely applied in embedded computing domains. However, the popularity of embedded applications and the improvement of chip integration impose more significant challenges on heterogeneous MPSoC design. The challenges include:1) how to improve the flexibility of heterogeneous MPSoC hardware platform to satisfy the frequently changing requirements of embedded applications,2) how to improve the utilization efficiency of processor cores to make full use of the performance potential of MPSoCs and,3) how to formally modeling heterogeneous MPSoCs, especially accurately describing their complicated characteristics of dynamic events, so as to assist designers to verify the correctness and evaluate the performance of system hardware/software designs.
This dissertation studies the above problems separately. The study and its innovative features involve:
1) In order to increase the system flexibility, we combine Dynamic Partial Reconfiguration (DPR) technology with Service-Oriented heterogeneous Multi-Processor (SOMP) architecture by providing a system hardware/software designing flow, an inter-module communication interface and a parallel programming model which support DPR. The SOMP prototyping system is implemented on a Field Programmable Gate Array (FPGA) based development board, which demonstrates the correctness of our proposed designing method. Besides, for demonstrating the effectiveness of DPR, the reconfiguration overhead of the prototyping system and the resource overhead introduced by DPR are also evaluated in this dissertation.
2) This dissertation extends Amdahl's law and applies it into heterogeneous MPSoCs. According to the extension, we quantitatively analyze the impacts on system performance of different factors, such as the configuration of processor cores, the proportion of parallelizable tasks and task partitioning strategy. Then we point out the conditions in theory which will lead to the maximum system performance. The extension is of guiding significance to design optimizing of heterogeneous MPSoCs and improving the system efficiency.
3) Fully revealing task level parallelism of applications is an efficient way of improving the utilization efficiency of multicore systems. To this end, the scheme for automatically parallelizing tasks is studied in this dissertation. By regarding tasks as abstract instructions, we extend instruction level scoreboarding algorithm to heterogeneous MPSoCs for the first time and propose a dynamical scheduling scheme named Task Level Scoreboarding (TLS). TLS can dynamically detect inter-task dependencies and automatically dispatch tasks to different cores to execute in parallel. Therefore, the task level parallelism of applications can be improved. TLS is implemented on the SOMP prototyping system and compared to other state-of-art dynamic scheduling schemes through experiments. The result of comparison demonstrates our proposed TLS introduces less runtime scheduling overhead.
4) This dissertation models heterogeneous MPSoCs using a formal modeling language, Colored Petri Nets (CPN). Unlike previous research work, the CPN model proposed in this dissertation can describe not only static elements of a system such as processor cores, memory units and tasks, but also dynamic events during system execution which includes detecting inter-task dependencies and task dispatching. So the model can be employed to model task execution process in a system and the corresponding scheduling algorithm. Assisted by the model, designers are able to evaluate the performance of heterogeneous MPSoC hardware/software designs as early as possible. This dissertation utilizes the model to simulate the SOMP prototyping system, together with out-of-order task execution processes on it. By comparing the result of model-based simulation and actual execution of the prototyping system, we demonstrate that the proposed CPN model can accurately simulate the execution of heterogeneous MPSoCs.
引文
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