Improved performance by using TaON/SiO₂ as dual tunnel layer in Charge-Trapping nonvolatile memory

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• 作者：J.X. Chen ; J.P. Xu ; L. Liu ; X.D. Huang ; P.T. Lai
• 刊名：Microelectronics Reliability
• 出版年：February, 2014
• 年：2014
• 卷：54
• 期：2
• 页码：393-396
• 全文大小：970 K

文摘

Tunneling-barrier engineered stacks with different high-魏 dielectrics are investigated by fabricating the stacked structures of Al/Al₂O₃/HfLaON/ (TaON/SiO₂)/Si and Al/Al₂O₃/HfLaON/ (HfON/SiO₂)/Si. As compared to the device with HfON/SiO₂ dual tunnel layer (DTL), the one with TaON/SiO₂ DTL shows larger memory window (3.85 V at 卤 13 V/1 s), higher program/erase speeds (1.85 V/鈭?.00 V at 卤 12 V/100 渭s), better endurance (window narrowing rate of 5.7% after 10⁵ cycles). The main mechanisms involved lie in (1) the higher dielectric constant of TaON which induces high electric field in the SiO₂ layer, (2) the smaller conduction/valence-band offsets between TaON and the Si substrate, and (3) better interface quality with SiO₂. Furthermore, compared with SiO₂ single tunnel layer, better retention characteristics can be achieved for the TaON/SiO₂ DTL due to its larger thickness.