Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs

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• 作者：Changliang Qin^a ; Guilei Wang^a ; Peizhen Hong^a ; Jinbiao Liu^a ; Huaxiang Yin^a ; ^{yinhuaxiang@ime.ac.cn" class="auth_mail" title="E-mail the corresponding author} ; Haizhou Yin^a ; Xiaolong Ma^a ; Hushan Cui^a ; Yihong Lu^a ; Lingkuan Meng^a ; Jinjuan Xiang^a ; Huicai Zhong^a ; Huilong Zhu^a ; Qiuxia Xu^a ; Junfeng Li^a ; Jian Yan^a ; Chao Zhao^a ; Henry H. Radamson^b
• 关键词：Mosfet ; SiGe ; Source/drain recess ; Epitaxy ; Source/drain extension implant ; 22  ; nm node
• 刊名：Solid State Electronics
• 出版年：2016
• 出版时间：September 2016
• 年：2016
• 卷：123
• 期：Complete
• 页码：38-43
• 全文大小：2520 K

文摘

In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF₂ in SiGe layers. The overlap space between doping junction and channel region has great effect on the device’s performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer I_D–V_G curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on–off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.