用户名: 密码: 验证码:
Novel Design for Reversible Arithmetic Logic Unit
详细信息    查看全文
  • 作者:Rigui Zhou (1)
    Yancheng Li (1)
    Manqun Zhang (1)
    BenQiong Hu (2)

    1. College of Information Engineering
    ; East China JiaoTong University ; 330013 ; Nanchang ; Jiangxi ; Peoples Republic of China
    2. College of Management Science
    ; Chengdu University of Technology ; Chengdu ; 610059 ; China
  • 关键词:Reversible logic ; Reversible ALU ; Quantum cost ; Quantum computer ; Toffoli gate
  • 刊名:International Journal of Theoretical Physics
  • 出版年:2015
  • 出版时间:February 2015
  • 年:2015
  • 卷:54
  • 期:2
  • 页码:630-644
  • 全文大小:1,025 KB
  • 参考文献:1. Burks, A.W., Goldstine, H.H., Von Neumann, J.: Preliminary Discussion of the Logical Design of an Electronic Computing Instrument[M]. Springer, Berlin Heidelberg (1982)
    2. Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183鈥?91 (1961). CrossRef
    3. Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17, 525鈥?32 (1973) CrossRef
    4. Babu, H.M.H., Islam, M.R., Chowdhury, A.R., Chowdhury, S.M.A.: Reversible logic synthesis for minimization of full-adder circuit. In: IEEE Conference of Digital System Desisn, pp. 50鈥?4 (2003)
    5. Maslov, D., Miller, D.M.: Comparison of the cost metrics through investigation or the relation between optimal NCV and optimal NCT three-qubit reversible circuits. IET Comput. Digit. Tech. 1(2), 98鈥?04 (2007) CrossRef
    6. Maslov, D., Dueck, G.W.: Garbage in reversible design of multiple output functions. In: 6th International Symposium on Representations and Methodology of Future Computing Technologies pp. 162鈥?70 (2003)
    7. Parhami, B.: Fault tolerant reversible circuits, In: Proceedings of the 40th Asilomar Conference on Signals Systems, and Computers. Pacific Grove (2006)
    8. Perkowski, M., Al-Rabadi, A., Kerntopf, P., Buller, A., Chrzanowska-Jeske, M., Mishchenko, A., Azad Khan, M., Coppola, A., Yanushkevich, S., Shmerko, V., Jozwiak, L.: A general decomposition for reversible logic. In: Proceedings of the RM 2001, pp. 119鈥?38. Starkville
    9. Michael, K.T., Robert, G., Holger, B.A.: Reversible arithmetic logic unit for quantum arithmetic. J. Phys. A: Math. Theor. 43(38), 2010 (2002)
    10. Thapliyal, H., Srinivas, M.B.: A novel reversible TSG gate and its application for designing reversible carry look ahead adder and other adder architectures. In: 10th Asia-Pacific Computer Systems Architecture Conference (2005)
    11. Zhou, R.G., Li, Y.C., Zhang, M.Q.: Novel designs for fault tolerant reversible binary coded decimal adders. In: International Journal of Electronics, pp. 1鈥?1 (ahead-of-print) (2013).
    12. Zhou, R., Zhang, M., Wu, Q., et al.: Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates[J]. Int. J. Electron. 99(10), 1395鈥?414 (2012) CrossRef
    13. Krishnaveni, D., Geetha P.M.: A novel design of reversible serial and parallel adder/subtractor. Int. J. Eng. Sci. Technol. (IJEST). 3(3), 2280鈥?288 (2010)
    14. Rigui, Z., Yang, S., Hui鈥檃n, W., Jian, C.: Transistor realization of reversible ZS series gates and reversible array multiplier. Microelectron. J. 42(2), 305鈥?15 (2011) CrossRef
    15. Thaplyal, H., Srinivas, M.B.: Novel reversible multiplier architecture using reversible TSG gate. In: IEEE International Conference of Computer Systems and Applications, pp. 100鈥?03, (2006)
    16. Peres, A.: Reversible logic and quantum computers. Phys. Rev., 3266鈥?276 (1985)
    17. Oskin, M., Chong, F.T., Chuang I.L.: A practical architecture for reliable quantum computers. Computer 35, 79鈥?7 (2002) CrossRef
    18. Biswas, A.K., Hasan, Md. M., Chowdhury, A.R.: Hafiz Md.Hasan Babu, Efficient approaches for designing reversible Binary Coded Decimal adders. Microelectron. J. 39, 1693鈥?703 (2008) CrossRef
    19. Hui, L., Zhijin, G., Shanli, C., Yuxin, C.: The reversible network cascade based on reversible logic gate coding method. In: Fifth International Conference on Information Assurance and Security, pp. 213-216 (2009)
    20. Feynman, R.: Quantum mechanical computers. Opt. News, 11鈥?0 (1985)
    21. Toffoli T: Reversible computing, Tech Memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980)
    22. Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge University Press, Cambridge (2000)
    23. Morrison, M., Ranganathan, N.: Design of a reversible ALU on novel programmable reversible logic gate structures. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 126鈥?31. IEEE (2011)
    24. Syamala, Y., Tilak, A.V.N.: Reversible arithmetic logic unit. In: 3rd International Conference on Electronics Computer Technology (ICECT), vol. 5, pp. 207鈥?11. IEEE (2011)
    25. Vieri, C., Josephine Ammer, M., Frank, M., Margolus, N., Knight, T.: A fully reversible asymptotically zero energy processor. In: Proceedings of the ISCA Workshop (1998)
    26. Morrison, M., Lewandowski, M., Meana, R., et al.: Design of a novel reversible alu using an enhanced carry look-ahead adder. In: 11th IEEE Conference on Nanotechnology (IEEE-NANO), pp. 1436鈥?440. IEEE (2011)
  • 刊物类别:Physics and Astronomy
  • 刊物主题:Physics
    Physics
    Quantum Physics
    Elementary Particles and Quantum Field Theory
    Mathematical and Computational Physics
  • 出版者:Springer Netherlands
  • ISSN:1572-9575
文摘
Reversible logic circuits are of high interests to calculate with minimum energy consumption having applications in low-power CMOS design, optical computing and nanotechnology, especially in quantum computer. Quantum computer requires quantum arithmetic. A new design of a reversible arithmetic logic unit (reversible ALU) for quantum arithmetic has been proposed in this article. As we known, ALU is an important part of central processing unit (CPU) as the execution unit. So this article provides explicit construction of reversible ALU effecting basic arithmetic operations. By provided the corresponding control unit, the proposed reversible ALU can combine the classical arithmetic and logic operation in a reversible integrated system. This article provides a new more powerful ALU which contains more functions and it will make contribute to the realization of reversible Programmable Logic Device (RPLD) in future using reversible ALU.

© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号

地址:北京市海淀区学院路29号 邮编:100083

电话:办公室:(+86 10)66554848;文献借阅、咨询服务、科技查新:66554700