用户名: 密码: 验证码:
保护环版图结构对ESD防护器件耐压能力的影响
详细信息    查看全文 | 推荐本文 |
  • 英文篇名:Impact of Guard Ring Layout Structure on the Voltage-Tolerance Capacity of ESD Protection Devices
  • 作者:刘畅 ; 黄鲁 ; 张峰
  • 英文作者:Liu Chang;Huang Lu;Zhang Feng;Department of Electronic Science and Technology,University of Science and Technology of China;National ASIC Design Engineering Center,Institute of Automation,Chinese Academy of Sciences;
  • 关键词:静电放电(ESD) ; 版图 ; 保护环 ; 多指器件非均匀开启 ; 传输线脉冲(TLP)测试 ; 耐压能力
  • 英文关键词:electrostatic discharge(ESD);;layout;;guard ring;;non-uniform turn-on of multifinger device;;transmission line pulse(TLP) testing;;voltage-tolerance capacity
  • 中文刊名:BDTJ
  • 英文刊名:Semiconductor Technology
  • 机构:中国科学技术大学电子科学与技术系;中国科学院自动化研究所国家专用集成电路设计工程技术研究中心;
  • 出版日期:2017-03-03
  • 出版单位:半导体技术
  • 年:2017
  • 期:v.42;No.343
  • 语种:中文;
  • 页:BDTJ201703009
  • 页数:5
  • CN:03
  • ISSN:13-1109/TN
  • 分类号:51-55
摘要
基于华润上华0.5μm双极-CMOS-DMOS(BCD)工艺设计制备了不同保护环分布情况下的叉指型内嵌可控硅整流器的横向扩散金属氧化物半导体(LDMOS-SCR)结构器件,并利用传输线脉冲(TLP)测试比较静电放电(ESD)防护器件的耐压能力。以LDMOS-SCR结构为基础,按照16指、8指、4指和2指设置保护环,形成4种不同类型的版图结构。通过器件的直流仿真分析多指器件的开启情况,利用传输线脉冲测试对比不同保护环版图结构的耐压能力。仿真和测试结果表明,改进后的3类版图结构相对于普遍通用的第一类版图结构,二次击穿电流都有所提升,其中每8指设置一个保护环的版图结构二次击穿电流提升了76.36%,其单位面积的鲁棒性能也最好,为相应工艺设计最高耐压值的ESD防护器件提供了参考结构和方法。
        A embedded multi-finger laterally diffused metal oxide semiconductor silicon-controlled rectifier( LDMOS-SCR) structural devices with different types of guard ring layout were designed and fabricated in a CSMC 0. 5 μm bipolar-CMOS-DMOS( BCD) process. And the transmission line pulse( TLP) testing was used to compare the voltage-tolerance capacity of these electrostatic discharge( ESD)protection devices. Based on the LDMOS-SCR structure,16,8,4 and 2 fingers were surrounded by guard rings,then four different guard ring layout structures were grouped. The turn-on condition of the multi-finger devices was analyzed by the direct-current simulation device,and the voltage-tolerance capacity of different guard ring layout structures were compared with the TLP testing. Simulation and test results show that the secondary breakdown current of three optimized types of layout structures are higher than that of the conventional one. The type whose eight fingers are surrounded by one guard ring provides76. 36% improvement of the secondary breakdown current,and has the strongest robustness per unit area.These devices can provide a reference structure and method for the design of highest voltage-tolerance ESD protection devices in the corresponding process.
引文
[1]VASHCHENKO V A,STRACHAN A,LINTEN D,et al.Improving the ESD self-protection capability of integrated power NLDMOS arrays[C]∥Proceedings of the IEEE 32ndElectrical Overstress/Electrostatic Discharge Symposium(EOS/ESD).2010:1-8.
    [2]KEPPENS B,MERGENS M P J,TRINH C S,et al.ESD protection solutions for high voltage technologies[J].Microelectronics Reliability,2006,46(5):677-688.
    [3]黄龙,梁海莲,顾晓峰,等.多晶硅栅对LDMOSSCR器件ESD防护性能的影响[J].浙江大学学报(工学版),2015(2):366-370.HUANG L,LIANG H L,GU X F,et al.Effect of poly-silicon gate on ESD protection performance of LDMOSSCR devices[J].Journal of Zhejiang University(Engineering Science),2015(2):366-370(in Chinese).
    [4]ZHENG J,HAN Y,WONG H,et al.Robust and areaefficient n LDMOS-SCR with waffle layout structure for high-voltage ESD protection[J].Electronics Letters,2012,48(25):1629-1630.
    [5]WANG Z X,LIOU J J.Evaluation of geometry layout and metal pattern to optimize ESD performance of silicon controlled rectifier(SCR)[C]∥Proceedings of IEEE International Reliability Physics Symposium.Waikoloa,HI,USA,2014:EL.2.1-EL.2.4.
    [6]CHEN S L,LIN C J,LEE M H,et al.Layout-type dependence on ESD/LU reliabilities for LVTn SCR devices[C]∥Proceedings of the IEEE 1stInternational Future Energy Electronics Conference.Tainan,Taiwan,China,2013:746-750.
    [7]LIU Z W,HE J,LIOU J J,et al.Segmented SCR for high voltage ESD protection[C]∥Proceedings of the IEEE 11thInternational Conference on Solid-State and Integrated Circuit Technology.Xi'an,China,2012:1-4.
    [8]LIAO S F,TANG K N,KER M D,et al.Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection[C]∥Proceedings of IEEE European Conference on Circuit Theory and Design.Trondheim,Norway,2015:1-4.

© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号

地址:北京市海淀区学院路29号 邮编:100083

电话:办公室:(+86 10)66554848;文献借阅、咨询服务、科技查新:66554700