多电源域高速IO的片上模块化ESD防护器件
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摘要
提出一种新颖的片上静电泄放(ESD)防护器件,该器件由N阱/P阱二极管、基于high-K金属栅CMOS工艺形成的二极管、寄生的晶闸管(SCR)和内嵌的电源钳位电路等几部分构成,具有多条ESD通路,能实现对单个IO管脚的PS-Mode、NS-Mode、PD-Mode、ND-Mode及DSMode共5种ESD应力模式的保护。本文分析了high-K工艺下各种SCR模块的结构和工作机制,通过合理配置这些SCR,该器件的一些关键ESD参数如触发电压、保持电压等能根据具体需要而调整,以满足片上系统(SoC)的多电源域的应用情况,利用传输线脉冲(TLP)、快速TLP和C-V等方式全方位验证了该器件的性能。结果表明,紧凑的结构、较少的互连线、较低的寄生电容、快速的响应能力使设计的器件适合高速IO接口电路的ESD防护。
A novel on-chip electrostatic discharge (ESD) protection device (NMMEPD) was proposed. This device consists of N-well/P-well diode,parasitic SCR (silicon-controlled rectifier),diode formed by high-K metal gate CMOS technology and embedded power clamp. There are multiple discharge paths in the proposed device,so it can achieve protection of 5 ESD stress modes for a single IO pin. Some details on the structure and working mechanism of various SCR modules under high-k process were analyzed and the modularization design was conducted. Some critical ESD parameters,such as the triggering voltage,holding voltage and etc.,can be flexibly adjusted via reasonable configuration modular SCR to satisfy the multi-power supply domain applications of SoC (System on Chip). The performance of the NMMEPD was validated comprehensively by means of the TLP,very-fast TLP and C-V. Experimental results showed that compact structure,less interconnect,low parasitic capacitance,and fast ESD stress response capabilities made the proposed device more suitable for high-speed IO interface circuit ESD protection application.
A novel on-chip electrostatic discharge (ESD) protection device (NMMEPD) was proposed. This device consists of N-well/P-well diode,parasitic SCR (silicon-controlled rectifier),diode formed by high-K metal gate CMOS technology and embedded power clamp. There are multiple discharge paths in the proposed device,so it can achieve protection of 5 ESD stress modes for a single IO pin. Some details on the structure and working mechanism of various SCR modules under high-k process were analyzed and the modularization design was conducted. Some critical ESD parameters,such as the triggering voltage,holding voltage and etc.,can be flexibly adjusted via reasonable configuration modular SCR to satisfy the multi-power supply domain applications of SoC (System on Chip). The performance of the NMMEPD was validated comprehensively by means of the TLP,very-fast TLP and C-V. Experimental results showed that compact structure,less interconnect,low parasitic capacitance,and fast ESD stress response capabilities made the proposed device more suitable for high-speed IO interface circuit ESD protection application.
引文
[1]李立.RFIC的ESD防护电路与优化设计技术研究[D].西安:西安电子科技大学,2012.LI L.Investigation of ESD protection circuit and optimaization design of RFIC[D].XI'an:Xidian University,2012.
[2]杜晓阳,CMOS射频集成电路片上ESD防护研究[D].杭州:浙江大学,2009.DU X Y.Investigation of on-chip ESD protection for CMOS RFIC[D].Hangzhou:Zhejiang University,2009.
[3]MATSUZAWA V.Analog and RF circuits design and future devices interaction[C]//Proc.IEEE IEDM,2012:14.3.1-14.3.4.
[4]YUNZHI D,SCHREIER R,YANG W,et al.A 235 m WCT 0-3 MASH ADC achieving-167 d BFS/Hz NSD with53 MHz BW[C]//Proc.IEEE ISSCC,IEEE,2014:480-481.
[5]CHEN J T,LIN C Y,KE M D.On-chip ESD protection device for high-speed I/O applications in CMOS technology[J].IEEE Transactions on Electron Devices,2017,64(10):3979-3985.
[6]SHI Z T,WANG X,LIU J,et al.Programmable on-chip ESD protection using nanocrystal dots mechanism and structures[J].IEEE Transactions on Nanotechnology,2012,11(5):884-889.
[7]CHEN S H,DIMITRI L,MIRKOSCHOLZ,et al.Local CDM ESD protection circuit for cross-power domains in3D IC applications[J].IEEE Transactions on Device and Materials Reliability,2014,14(2):781-783.
[8]LUO S R,SALCODO J A,PARTHASARATHY S,et al.In situ ESD protection structure for variable operating voltage interface applications in 28-nm CMOSprocess[J].IEEE Transactions on Device and Materials Reliability,2014,14(4):1061-1067.
[9]WORLEY E.Distributed gate ESD network architecture for inter-power domain signals[C]//Proc.EOS/ESDSymposium,2004:1-10.
[10]SEMENOV O,SARBISHAEI H,MANOJSACHDEY.ESD protection device and circuit design for advanced CMOS technologies[M].Berlin:Springer,2008.
[11]TZU-HENG C,HSU Y,TSAI T,et al.High-K metal gate-bounded silicon controlled rectifier for ESD protection[C]//Electrical Overstress/Electrostatic Discharge(EOS/ESD)Symposium,IEEE,2012:1-7.
[12]KER M D.ESD technology[EB/OL].(2017-06-11)[2018-08-25].http://www.ics.ee.nctu.edu.tw/~mdker/ESD/index/index1.html-index10.html.
[13]SALCEDO J A,PARTHASARATHY S,HAJJAR J J.Monolithic ESD protectionfor distributed high speed applications in 28-nm CMOS technology[C]//Proc.IEEE IRPS,IEEE,2014:4C.3.1-4C.3.4.
[14]WANG Z X,SUN R C,LIOU J J,et al.Optimized p MOS-triggered bidirectional SCR for low-voltage ESDprotection applications[J].IEEE Transactions on Electron Devices,2014,61(7):2588-2593.
[15]HUO M X,HAN Y,LI Y,et al.Study of turn-on characteristics of SCRs for ESD protection with TDR-O and TDR-S TLPs[C]//17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.Singapore:IEEE,2010:1-8.
[2]杜晓阳,CMOS射频集成电路片上ESD防护研究[D].杭州:浙江大学,2009.DU X Y.Investigation of on-chip ESD protection for CMOS RFIC[D].Hangzhou:Zhejiang University,2009.
[3]MATSUZAWA V.Analog and RF circuits design and future devices interaction[C]//Proc.IEEE IEDM,2012:14.3.1-14.3.4.
[4]YUNZHI D,SCHREIER R,YANG W,et al.A 235 m WCT 0-3 MASH ADC achieving-167 d BFS/Hz NSD with53 MHz BW[C]//Proc.IEEE ISSCC,IEEE,2014:480-481.
[5]CHEN J T,LIN C Y,KE M D.On-chip ESD protection device for high-speed I/O applications in CMOS technology[J].IEEE Transactions on Electron Devices,2017,64(10):3979-3985.
[6]SHI Z T,WANG X,LIU J,et al.Programmable on-chip ESD protection using nanocrystal dots mechanism and structures[J].IEEE Transactions on Nanotechnology,2012,11(5):884-889.
[7]CHEN S H,DIMITRI L,MIRKOSCHOLZ,et al.Local CDM ESD protection circuit for cross-power domains in3D IC applications[J].IEEE Transactions on Device and Materials Reliability,2014,14(2):781-783.
[8]LUO S R,SALCODO J A,PARTHASARATHY S,et al.In situ ESD protection structure for variable operating voltage interface applications in 28-nm CMOSprocess[J].IEEE Transactions on Device and Materials Reliability,2014,14(4):1061-1067.
[9]WORLEY E.Distributed gate ESD network architecture for inter-power domain signals[C]//Proc.EOS/ESDSymposium,2004:1-10.
[10]SEMENOV O,SARBISHAEI H,MANOJSACHDEY.ESD protection device and circuit design for advanced CMOS technologies[M].Berlin:Springer,2008.
[11]TZU-HENG C,HSU Y,TSAI T,et al.High-K metal gate-bounded silicon controlled rectifier for ESD protection[C]//Electrical Overstress/Electrostatic Discharge(EOS/ESD)Symposium,IEEE,2012:1-7.
[12]KER M D.ESD technology[EB/OL].(2017-06-11)[2018-08-25].http://www.ics.ee.nctu.edu.tw/~mdker/ESD/index/index1.html-index10.html.
[13]SALCEDO J A,PARTHASARATHY S,HAJJAR J J.Monolithic ESD protectionfor distributed high speed applications in 28-nm CMOS technology[C]//Proc.IEEE IRPS,IEEE,2014:4C.3.1-4C.3.4.
[14]WANG Z X,SUN R C,LIOU J J,et al.Optimized p MOS-triggered bidirectional SCR for low-voltage ESDprotection applications[J].IEEE Transactions on Electron Devices,2014,61(7):2588-2593.
[15]HUO M X,HAN Y,LI Y,et al.Study of turn-on characteristics of SCRs for ESD protection with TDR-O and TDR-S TLPs[C]//17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.Singapore:IEEE,2010:1-8.
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