功率NLDMOS电学安全工作区的版图设计优化
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摘要
在不调整制备工艺、不增加工艺成本条件下,研究了管芯版图优化对功率n型横向扩散金属氧化物半导体(NLDMOS)电学安全工作区(E-SOA)的影响。通过研究p~+带嵌入方式、p~+图形形状、p~+分布密度、阵列单元栅宽及总栅数、金属引线方式等进行了版图设计优化和流片。管芯传输线脉冲(TLP)E-SOA测试结果表明,优化后的版图使NLDMOS在5 V工作电压下TLP E-SOA提升约30%,金属引线的加宽和叠加使NLDMOS的开态电流提升约7%。带状紧凑型p~+带且双栅极嵌入的优化版图设计能更好地稳定硅衬底电位,抑制寄生三极管的开启,增大E-SOA,提高器件可靠性。因此,版图设计优化对提升功率NLDMOS的性能和可靠性具有实际意义。
The effects of layout optimization on the electrical safe operating area(E-SOA) of the power n-type laterally diffused metal oxide semiconductor(NLDMOS) were studied without adjusting fabrication process and increasing process cost. The layout design optimization and chip fabrication were carried out by studying the p~+ band embedding ways, p~+ pattern shapes, p~+ distribution densities, array cell gate width and total gate numbers, metal lead ways and so on. The transmission line pulse(TLP) E-SOA test results show that the optimized layout improves the TLP E-SOA of the NLDMOS by about 30% at the operating voltage of 5 V, and the widening and stack of the metal leads increase the on-state current of the NLDMOS by about 7%. The strip-shaped compact-type p~+ band and dual-gate fingers embedded optimized layout design can better stabilize the silicon substrate potential, suppress the opening of the parasi-tic transistor, increase the E-SOA, and improve the reliability of the device. Therefore, layout design optimization has practical significance for improving the performance and reliability of the power NLDMOS.
The effects of layout optimization on the electrical safe operating area(E-SOA) of the power n-type laterally diffused metal oxide semiconductor(NLDMOS) were studied without adjusting fabrication process and increasing process cost. The layout design optimization and chip fabrication were carried out by studying the p~+ band embedding ways, p~+ pattern shapes, p~+ distribution densities, array cell gate width and total gate numbers, metal lead ways and so on. The transmission line pulse(TLP) E-SOA test results show that the optimized layout improves the TLP E-SOA of the NLDMOS by about 30% at the operating voltage of 5 V, and the widening and stack of the metal leads increase the on-state current of the NLDMOS by about 7%. The strip-shaped compact-type p~+ band and dual-gate fingers embedded optimized layout design can better stabilize the silicon substrate potential, suppress the opening of the parasi-tic transistor, increase the E-SOA, and improve the reliability of the device. Therefore, layout design optimization has practical significance for improving the performance and reliability of the power NLDMOS.
引文
[1] SHIBIB A,LORENZ L,OHASHI H.30 year journey in advancing power semiconductor technology [C] ∥ Proceedings of the 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Chicago,IL,USA,2018:1-7.
[2] ZHAO Z Q,CAI C F,WANG T.Application opportunities and expectations for wide bandgap power devices in power supply [C] ∥ Proceedings of the 29th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Sapporo,Japan,2017:13-18.
[3] WILLEMEN J,JOHNSSON D,CAO Y Q,et al.A TLP-based characterization method for transient gate biasing of MOS devices in high-voltage technologies [C] ∥ Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).Reno,NE,USA,2010:1-10.
[4] HOWER P L,PENDHARKAR S.Short and long-term safe operating area considerations in NLDMOS transistors [C] ∥ Proceedings of the International Reliability Physics Symposium.San Jose,CA,USA,2005:545-550.
[5] YE R,LIU S Y,DAI Z G,et al.ESD failure analysis and robustness improvement for multi-STI-finger NLDMOS used as output device [C] ∥ Proceedings of the 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Chicago,IL,USA,2018:339-342.
[6] NIDHI K,KER M D,LIN T Y,et al.Improving safe-operating-area of a 5-V n-channel large array MOSFET in a 0.15-μm BCD process [J].Transactions on Electron Devices,2018,65(7):2948-2956.
[7] VASHCHENKO V A,HOPPER P J.A new principle for a self-protecting power transistor array design [C] ∥ Proceedings of the 18th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Naples,Italy,2006:1-4.
[8] HOWER P L.Safe operating area—a new frontier in NLDMOS design [C] ∥ Proceedings of the 14th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Sante Fe,NM,USA,2002:1-8.
[9] JARARD D T,AHMED S,VROTSOS T,et al.Electrical safe operating area of low-voltage silicon carbide NMOS transistors [C] ∥ Proceedings of the 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA) .Fayetteville,AR,USA,2016:236-241.
[10] DUAN B X,CAO Z,YUAN X N,et al.New super junction NLDMOS breaking silicon limit by electric field modulation of buffered step doping [J].IEEE Electron Device Letters,2015,36(1):47-49.
[2] ZHAO Z Q,CAI C F,WANG T.Application opportunities and expectations for wide bandgap power devices in power supply [C] ∥ Proceedings of the 29th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Sapporo,Japan,2017:13-18.
[3] WILLEMEN J,JOHNSSON D,CAO Y Q,et al.A TLP-based characterization method for transient gate biasing of MOS devices in high-voltage technologies [C] ∥ Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).Reno,NE,USA,2010:1-10.
[4] HOWER P L,PENDHARKAR S.Short and long-term safe operating area considerations in NLDMOS transistors [C] ∥ Proceedings of the International Reliability Physics Symposium.San Jose,CA,USA,2005:545-550.
[5] YE R,LIU S Y,DAI Z G,et al.ESD failure analysis and robustness improvement for multi-STI-finger NLDMOS used as output device [C] ∥ Proceedings of the 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Chicago,IL,USA,2018:339-342.
[6] NIDHI K,KER M D,LIN T Y,et al.Improving safe-operating-area of a 5-V n-channel large array MOSFET in a 0.15-μm BCD process [J].Transactions on Electron Devices,2018,65(7):2948-2956.
[7] VASHCHENKO V A,HOPPER P J.A new principle for a self-protecting power transistor array design [C] ∥ Proceedings of the 18th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Naples,Italy,2006:1-4.
[8] HOWER P L.Safe operating area—a new frontier in NLDMOS design [C] ∥ Proceedings of the 14th International Symposium on Power Semiconductor Devices and ICs (ISPSD).Sante Fe,NM,USA,2002:1-8.
[9] JARARD D T,AHMED S,VROTSOS T,et al.Electrical safe operating area of low-voltage silicon carbide NMOS transistors [C] ∥ Proceedings of the 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA) .Fayetteville,AR,USA,2016:236-241.
[10] DUAN B X,CAO Z,YUAN X N,et al.New super junction NLDMOS breaking silicon limit by electric field modulation of buffered step doping [J].IEEE Electron Device Letters,2015,36(1):47-49.
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