面向航天应用的高可靠性FPGA动态局部重构
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摘要
在航天应用中,FPGA的单粒子翻转是影响航天器功能和寿命的重要因素,目前,部分航天产品使用定时重加载的方式避免单粒子效应的积累和影响,但是重加载的过程会导致全部FPGA逻辑中断,极大影响航天器功能的持续性。因此,文章提出了一种适用于航天的FPGA动态局部重配置系统,在阐述了FPGA动态局部重配置技术的原理和航天应用前景后,详细说明了其设计流程、硬件电路板架构和控制软件框图。通过板级试验验证了系统功能,采用示波器对结果进行了测试,证明该系统设计的高可靠性。FPGA动态局部重配置技术,既提高了FPGA的可靠性,又保证了FPGA部分关键功能的持续性。
In aerospace applications, the single event flipping of FPGA is an important factor affecting the function and lifetime of the spacecraft. At present, the time reloading method is applied to avoid the accumulation and influence of the single event effect in some of the aerospace products. However, the reloading process will lead to all FPGA logic interruptions, which greatly affects the sustainability of the spacecraft's functions. Therefore, a FPGA dynamic partial reconfiguration system for aerospace applications is proposed in this paper. The principle of FPGA dynamic partial reconfiguration technology and its prospect in space application are expounded firstly. Then the design process, the hardware circuit board architecture and the control software block diagram are described in detail. The function of the system is verified by the plate test,and the result tested by the oscilloscope demonstrates that the design of the system has high reliability. The FPGA dynamic partial reconfiguration technology proposed in this paper not only improves the reliability of the FPGA, but also ensures the sustainability of some key functions of the FPGA.
In aerospace applications, the single event flipping of FPGA is an important factor affecting the function and lifetime of the spacecraft. At present, the time reloading method is applied to avoid the accumulation and influence of the single event effect in some of the aerospace products. However, the reloading process will lead to all FPGA logic interruptions, which greatly affects the sustainability of the spacecraft's functions. Therefore, a FPGA dynamic partial reconfiguration system for aerospace applications is proposed in this paper. The principle of FPGA dynamic partial reconfiguration technology and its prospect in space application are expounded firstly. Then the design process, the hardware circuit board architecture and the control software block diagram are described in detail. The function of the system is verified by the plate test,and the result tested by the oscilloscope demonstrates that the design of the system has high reliability. The FPGA dynamic partial reconfiguration technology proposed in this paper not only improves the reliability of the FPGA, but also ensures the sustainability of some key functions of the FPGA.
引文
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[8]赵秋桂,段青亚.FPGA动态局部可重构中基于TBUF总线宏设计[J].现代电子技术,2009,32(12):22-24.ZHAO Qiugui,DUAN Qingya.Design of Bus Macro-based TBUF for FPGA Dynamic Reconfiguration[J].Modern Electronics Technique,2009,32(12):22-24.(in Chinese)
[9]CHOW P,SEO S O,ROSE J,et a1.The Design of an SRAM-based Field-programmable Gate Array-Part I:Architecture[J].IEEE Transactions on VLSI Systems.1999,7(2):191-197.
[10]WOLF W,JERRAYA A A,MARTIN G.Multiprocessor System-on-chip Technology[J].IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,2008,27(10):1701-1713.
[11]冯晓静,李曦,王超,等.支持动态部分重构特性的异构多核体系结构[J].中国科学技术大学学报,2014,44(4):310-316.FENG Xiaojing,LI Xi,WANG Chao,et al.A Multiprocessor Architecture Supporting Dynamic Partial Reconfiguration[J].Journal of University of Science and Technology of China,2014,44(4):310-316.(in Chinese)
[12]WATKINS M A,ALBONESI D H.ReMAP:A Reconfigurable Heterogeneous Multicore Architecture[C]//43rd Annual IEEE/ACM International Symposium on Microarchitecture.Atlanta,USA:IEEE Press,2010:497-508.
[2]薛建伟,张杰,关永.基于EAPR流程的动态局部可重构实现[J].计算机工程,2010,36(23):252-254.XUE Jianwei,ZHANG Jie,GUAN Yong.Implementation of Dynamic Partial Reconfiguration Based on EARP Flow[J].Computer Engineering,2010,36(23):252-254.(in Chinese)
[3]TODMAN T J,CONSTANTINIDES G A,WILTON S J E.et al.Reconfigurable Computing:Architectures and Design Methods[J].IEEE Proceedings-Computers and Digital Techniques,2005,152(2):193-207.
[4]CHAMBERLAIN R D,FRANKLIN M A,TYSON E J,et al.Auto-pipe:Streaming Applications on Architecturally Diverse Systems[J].Computer,2010,43(3):42-49.
[5]徐新民,乐莹,尚丽娜.FPGA动态部分重构的研究及位流信息重构的实现[J].科技通报,2008,24(2):235-240.XU Xinmin,LE Ying,SHANG Lina.The Research on Partially Dynamic Reconfiguration for FPGA and Its Implementation Based on Bitstream[J].Bulletin of Science and Technology,2008,24(2):235-240.(in Chinese)
[6]DEHON H,MARKOVSHY Y,CASPI E,et al.Stream Computation Organized for Reconfigurable Execution[J].Reconfigurable Computing,2008,30(6):203-218.
[7]范斌,常青.基于DSP的FPGA动态重构系统研究与设计[J].信息与电子工程,2010,8(2):123-127.FAN Bin,CHANG Qing.Dynamically Reconfigurable System of FPGA Based on DSP[J].Information and Electronic Engineering,2010,8(2):123-127.(in Chinese)
[8]赵秋桂,段青亚.FPGA动态局部可重构中基于TBUF总线宏设计[J].现代电子技术,2009,32(12):22-24.ZHAO Qiugui,DUAN Qingya.Design of Bus Macro-based TBUF for FPGA Dynamic Reconfiguration[J].Modern Electronics Technique,2009,32(12):22-24.(in Chinese)
[9]CHOW P,SEO S O,ROSE J,et a1.The Design of an SRAM-based Field-programmable Gate Array-Part I:Architecture[J].IEEE Transactions on VLSI Systems.1999,7(2):191-197.
[10]WOLF W,JERRAYA A A,MARTIN G.Multiprocessor System-on-chip Technology[J].IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,2008,27(10):1701-1713.
[11]冯晓静,李曦,王超,等.支持动态部分重构特性的异构多核体系结构[J].中国科学技术大学学报,2014,44(4):310-316.FENG Xiaojing,LI Xi,WANG Chao,et al.A Multiprocessor Architecture Supporting Dynamic Partial Reconfiguration[J].Journal of University of Science and Technology of China,2014,44(4):310-316.(in Chinese)
[12]WATKINS M A,ALBONESI D H.ReMAP:A Reconfigurable Heterogeneous Multicore Architecture[C]//43rd Annual IEEE/ACM International Symposium on Microarchitecture.Atlanta,USA:IEEE Press,2010:497-508.
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