新型基区结构高反压功率晶体管的优化
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摘要
依据电参数指标要求,针对高压-高增益硅功率晶体管基区结构和终端结构进行优化研究。提出了一种可用于改善集电极-发射极击穿电压(V_((BR)CEO))和电流放大倍数(β)矛盾关系的带埋层的新型基区结构,并针对埋层基区结构对高压-高增益硅功率晶体管电性能及可靠性的影响进行了研究。仿真结果表明:新型基区结构不仅可以很好地折中晶体管β与V_((BR)CEO)之间的矛盾关系,而且还能在较大的埋层基区宽度、埋层基区掺杂峰值浓度范围内使晶体管获得较低且一致性较好的饱和压降;具有新型基区结构的晶体管在改善正偏的情况下抗二次击穿能力具有明显优势。由仿真得到的器件结构参数,研制出的样片的β,V_((BR)CEO)和集电极-基极击穿电压(V_((BR)CBO))均满足电参数指标要求。
According to the electrical parameter requirements, the optimization of the base structure and terminal structure of high-voltage and high-gain silicon power transistor was studied. A new base structure with buried layer which can improve the contradiction between the collector-emitter breakdown voltage(V_((BR)CEO)) and the current amplification(β) was proposed. In addition, the influences of the buried layer structure on the electrical performance and reliability of high-voltage and high-gain silicon power transistors were studied. The simulation results show that the new base structure can compromise the contradiction between β and V_((BR)CEO), and achieve a low and consistent saturation voltage drop within a larger range of width and the peak doping concentration of the buried base region. The transistor with new base structure has an obvious advantage in resisting the secondary breakdown under the condition of improving positive bias. According to the device structure parameters obtained by simulation,β, V_((BR)CEO) and collector base breakdown voltage(V_((BR)CBO)) of the sample meet the requirements of the electrical parameters.
According to the electrical parameter requirements, the optimization of the base structure and terminal structure of high-voltage and high-gain silicon power transistor was studied. A new base structure with buried layer which can improve the contradiction between the collector-emitter breakdown voltage(V_((BR)CEO)) and the current amplification(β) was proposed. In addition, the influences of the buried layer structure on the electrical performance and reliability of high-voltage and high-gain silicon power transistors were studied. The simulation results show that the new base structure can compromise the contradiction between β and V_((BR)CEO), and achieve a low and consistent saturation voltage drop within a larger range of width and the peak doping concentration of the buried base region. The transistor with new base structure has an obvious advantage in resisting the secondary breakdown under the condition of improving positive bias. According to the device structure parameters obtained by simulation,β, V_((BR)CEO) and collector base breakdown voltage(V_((BR)CBO)) of the sample meet the requirements of the electrical parameters.
引文
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[2] NAWAZ M, CHEN N, CHIMENTO F, et al. Static and dynamic characterization of high power silicon carbide BJT modules [C]//Proceedings of IEEE Energy Conversion Congress and Exposition. Pittsburgh, PA, USA, 2014: 2824-2831.
[3] DORIDANT A, JARRIX S, RAOULT J, et al. Impact of total ionizing dose on the electromagnetic susceptibility of a single bipolar transistor[J]. IEEE Transactions on Nuclear Science, 2012, 59(4):860-865.
[4] 刘洪军,王建浩,丁晓明.1.2～1.4 GHz 370 W硅双极型晶体管研制[J].固体电子学研究与进展,2014,34(2):124-128.LIU H J, WANG J H, DING X M. Development of 1.2～1.4 GHz 370 W silicon bipolar transistor[J].Resear-ch & Progress of SSE,2014,34(2):124-128 (in Chinese).
[5] 陈祖良, 岳巍, 李兆龙, 等. 电子辐照改善双极型开关晶体管反向击穿特性[J]. 半导体技术, 2014, 39(12):943-946.CHEN Z L, YUE W, LI Z L, et al. Improvement on reverse breakdown characteristics of the bipolar switching transistor by the electron irradiation [J]. Semiconductor Technology, 2014, 39(12):943-946 (in Chinese).
[6] FEKRI M, MOLAVI N, ADIB E, et al. High voltage gain interleaved DC-DC converter with minimum current ripple[J]. IET Power Electronics, 2017, 10(14):1924-1931.
[7] 董果香. 半导体器件物理参数模型研究及器件模拟[D]. 成都:电子科技大学, 2013.
[8] KHANNA V K, KUMAR A, MAJ B, et al. Physical insight into Thermal behaviour of power DMOSFET and IGBT: a two-dimensional computer simulation study[J]. Physica Status Solidi, 2001, 185(2):309-329.
[9] 陈星弼,张庆中.晶体管原理与设计[M]. 2版.北京:电子工业出版社,2006:150-153.
[10] 刘铭,冯全源,陈晓培,等.一款800 V VDMOS终端结构的设计[J]. 电子元件与材料, 2015, 34(6):66-69.LIU M, FENG Q Y, CHEN X P, et al. Design of an 800 V VDMOS termination structure [J]. Electronic Components and Materials, 2015, 34 (6):66-69 (in Chinese).
[11] 徐建丽, 夏婷婷. 功率半导体器件击穿特性及结终端结构参数研究[J]. 硅酸盐通报, 2018, 37(6):2067-2072, 2078.XU J L, XIA T T. Breakdown characteristics and junction termination structural parameters of power semiconductor devices [J]. Bulletin of the Chinese Ceramic Society, 2018, 37(6):2067-2072, 2078 (in Chinese).
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