多核处理器发展趋势及关键技术
|
摘要
由处理器从单核向多核发展及多核处理器从同构向异构发展两个角度,分析处理器的发展历程,阐述导致处理器从单核向多核发展的两个关键问题。通过对同构多核处理器与异构多核处理器的结构特征、性能特点和典型代表的分析,总结处理器向异构多核的方向发展的趋势;对多核处理器核间通信、任务调度、Cache一致性、核间同步与互斥、核间中断处理机制这五大关键技术进行分析;提出当前多核处理器技术面临的三大问题。
Processors have developed from single-core to multi-core and so did multi-core processors from homogeneous to heterogeneous.From these two angles,the development trend of multi-core processor was analyzed and two key questions for why processors develop from single-core to multi-core were elaborated.Through analyzing the structure characteristics,performance characteristics and typical representatives of homogeneous multi-core processors and heterogeneous multi-core processors,the development trend of the processor was summarized.The five key technologies of multi-core processor,such as inter core communication,task scheduling,Cache consistency,inter core synchronization and mutual exclusion as well as interrupt mechanism,were analyzed.Three major issues that the current multi-core processor technology faces were raised.
Processors have developed from single-core to multi-core and so did multi-core processors from homogeneous to heterogeneous.From these two angles,the development trend of multi-core processor was analyzed and two key questions for why processors develop from single-core to multi-core were elaborated.Through analyzing the structure characteristics,performance characteristics and typical representatives of homogeneous multi-core processors and heterogeneous multi-core processors,the development trend of the processor was summarized.The five key technologies of multi-core processor,such as inter core communication,task scheduling,Cache consistency,inter core synchronization and mutual exclusion as well as interrupt mechanism,were analyzed.Three major issues that the current multi-core processor technology faces were raised.
引文
[1]Tran AT.On-chip network designs for many-core computational platforms[D].Sacramento:University of California,2012:1-4.
[2]Sawalha LH.Exploiting heterogeneous multicore processors through fine-grained scheduling and low-overhead thread migration[D].Oklahoma:The University of Oklahoma,2012:4-25.
[3]Koppanalil J,Yeung G,O’Driscoll D,et al.A 1.6GHz dualcore ARM cortex A9implementation on a low power high-K metal gate 32nm process[C]//International Symposium on Vlsi Design,Automation and Test.IEEE,2011:1-4.
[4]Abellan JL,Ros A,Fernandez J,et al.ECONO:Express coherence notifications for efficient cache coherency in many-core CMPs[C]//International Conference on Embedded Computer Systems:Architectures,Modeling,and Simulation.NJ:IEEE,2013:237-244.
[5]Hart JM,Cho H,Ge Y,et al.A 3.6GHz 16-core SPARC SoC Processor in 28nm[J].IEEE Journal of Solid-State Circuits,2014,49(1):19-31.
[6]Zhou R,Chen H,Liu Q,et al.A server model for reliable communication on cell/B.E.[C]//International Conference on Parallel Processing.IEEE Computer Society,2013:1020-1027.
[7]Greenhalgh P.Big.little processing with arm cortex-a15&cortex-a7[J].ARM White Paper,2011,1(1):1-8.
[8]Ananthanarayanan G,Malhotra G,Balakrishnan M,et al.Amdahl’s law in the era of process variation[J].International Journal of High Performance Systems Architecture,2013,4(4):218-230.
[9]Ganguly A,Chang K,Deb S,et al.Scalable hybrid wireless network-on-chip architectures for multicore systems[J].IEEE Transactions on Computers,2011,60(60):1485-1502.
[10]GENG Xiaozhong.Research on key techniques of task scheduling based on multi-core distributed environment[D].Changchun:Jilin University,2013:14-20(in Chinese).[耿晓中.基于多核分布式环境下的任务调度关键技术研究[D].长春:吉林大学,2013:14-20.]
[11]Barthou D,Jeannot E.SPAGHETtI:Scheduling/placement approach for task-graphs on heterogeneous architecture[M]//Euro-Par 2014Parallel Processing.Springer International Publishing,2014:174-185.
[12]Chronaki K,Rico A,Badia RM,et al.Criticality-aware dynamic task scheduling for heterogeneous architectures[C]//ACM on International Conference on Supercomputing,205:329-338.
[13]Bournoutian G,Orailoglu A.Dynamic,multi-core cache coherence architecture for power-sensitive mobile processors[C]//International Conference on Hardware/Software Codesign and System Synthesis.IEEE,2011:89-97.
[14]Chaturvedi N,Sharma P,Gurunarayanan S.An adaptive coherence protocol with adaptive cache for multi-core architectures[C]//International Conference on Advanced Electronic Systems.IEEE,2013:197-201.
[15]Hu Q,Wu K,Liu P.Exploiting multi-band transmission line interconnects to improve the efficiency of cache coherence in multiprocessor system-on-chip[C]//IEEE International System-on-Chip Conference.IEEE,2015.
[16]KONG Shuaishuai.Communication and interrupt researches based on embedded multicore processor[D].Chengdu:University of Electronic Science and Technology of China,2011:7-25(in Chinese).[孔帅帅.基于嵌入式多核处理器的通信及中断问题的研究[D].成都:电子科技大学,2011:7-25.]
[17]Lee PPC,Tian B,Chandranmenon G.A lock-free,cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring[C]//IEEE International Symposium on Parallel&Distributed Processing.IEEE,2010:1-12.
[18]LI Jiaojiao.Design and implementation of the main modules for operating system running on SMP processor platform[D].Xi’an:Xidian University,2012:47-51(in Chinese).[李娇娇.面向SMP架构处理器平台操作系统主要模块的设计与实现[D].西安:西安电子科技大学,2012:47-51.]
[19]WAN Xiaoyang,LI Yong,LUO Bo.Design and implementation of multicore DSP interrupt system based on M-DSP[C]//Microprocessor Technology Forum,2014:1-6(in Chinese).[万晓阳,李勇,罗波.基于M-DSP的多核DSP中断系统的设计与实现[C]//微处理器技术论坛,2014:1-6.]
[20]Hung SH,Tu CH,Yang WL.A portable,efficient intercore communication scheme for embedded multicore platforms[J].Journal of Systems Architecture,2011,57(2):193-205.
[21]GrayI,Audsley NC.Challenges in software development for multicore system-on-chip development[C]//23rd IEEE International Symposium on Rapid System Prototyping.IEEE,2012:115-121.
[2]Sawalha LH.Exploiting heterogeneous multicore processors through fine-grained scheduling and low-overhead thread migration[D].Oklahoma:The University of Oklahoma,2012:4-25.
[3]Koppanalil J,Yeung G,O’Driscoll D,et al.A 1.6GHz dualcore ARM cortex A9implementation on a low power high-K metal gate 32nm process[C]//International Symposium on Vlsi Design,Automation and Test.IEEE,2011:1-4.
[4]Abellan JL,Ros A,Fernandez J,et al.ECONO:Express coherence notifications for efficient cache coherency in many-core CMPs[C]//International Conference on Embedded Computer Systems:Architectures,Modeling,and Simulation.NJ:IEEE,2013:237-244.
[5]Hart JM,Cho H,Ge Y,et al.A 3.6GHz 16-core SPARC SoC Processor in 28nm[J].IEEE Journal of Solid-State Circuits,2014,49(1):19-31.
[6]Zhou R,Chen H,Liu Q,et al.A server model for reliable communication on cell/B.E.[C]//International Conference on Parallel Processing.IEEE Computer Society,2013:1020-1027.
[7]Greenhalgh P.Big.little processing with arm cortex-a15&cortex-a7[J].ARM White Paper,2011,1(1):1-8.
[8]Ananthanarayanan G,Malhotra G,Balakrishnan M,et al.Amdahl’s law in the era of process variation[J].International Journal of High Performance Systems Architecture,2013,4(4):218-230.
[9]Ganguly A,Chang K,Deb S,et al.Scalable hybrid wireless network-on-chip architectures for multicore systems[J].IEEE Transactions on Computers,2011,60(60):1485-1502.
[10]GENG Xiaozhong.Research on key techniques of task scheduling based on multi-core distributed environment[D].Changchun:Jilin University,2013:14-20(in Chinese).[耿晓中.基于多核分布式环境下的任务调度关键技术研究[D].长春:吉林大学,2013:14-20.]
[11]Barthou D,Jeannot E.SPAGHETtI:Scheduling/placement approach for task-graphs on heterogeneous architecture[M]//Euro-Par 2014Parallel Processing.Springer International Publishing,2014:174-185.
[12]Chronaki K,Rico A,Badia RM,et al.Criticality-aware dynamic task scheduling for heterogeneous architectures[C]//ACM on International Conference on Supercomputing,205:329-338.
[13]Bournoutian G,Orailoglu A.Dynamic,multi-core cache coherence architecture for power-sensitive mobile processors[C]//International Conference on Hardware/Software Codesign and System Synthesis.IEEE,2011:89-97.
[14]Chaturvedi N,Sharma P,Gurunarayanan S.An adaptive coherence protocol with adaptive cache for multi-core architectures[C]//International Conference on Advanced Electronic Systems.IEEE,2013:197-201.
[15]Hu Q,Wu K,Liu P.Exploiting multi-band transmission line interconnects to improve the efficiency of cache coherence in multiprocessor system-on-chip[C]//IEEE International System-on-Chip Conference.IEEE,2015.
[16]KONG Shuaishuai.Communication and interrupt researches based on embedded multicore processor[D].Chengdu:University of Electronic Science and Technology of China,2011:7-25(in Chinese).[孔帅帅.基于嵌入式多核处理器的通信及中断问题的研究[D].成都:电子科技大学,2011:7-25.]
[17]Lee PPC,Tian B,Chandranmenon G.A lock-free,cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring[C]//IEEE International Symposium on Parallel&Distributed Processing.IEEE,2010:1-12.
[18]LI Jiaojiao.Design and implementation of the main modules for operating system running on SMP processor platform[D].Xi’an:Xidian University,2012:47-51(in Chinese).[李娇娇.面向SMP架构处理器平台操作系统主要模块的设计与实现[D].西安:西安电子科技大学,2012:47-51.]
[19]WAN Xiaoyang,LI Yong,LUO Bo.Design and implementation of multicore DSP interrupt system based on M-DSP[C]//Microprocessor Technology Forum,2014:1-6(in Chinese).[万晓阳,李勇,罗波.基于M-DSP的多核DSP中断系统的设计与实现[C]//微处理器技术论坛,2014:1-6.]
[20]Hung SH,Tu CH,Yang WL.A portable,efficient intercore communication scheme for embedded multicore platforms[J].Journal of Systems Architecture,2011,57(2):193-205.
[21]GrayI,Audsley NC.Challenges in software development for multicore system-on-chip development[C]//23rd IEEE International Symposium on Rapid System Prototyping.IEEE,2012:115-121.