一种应用于大阵列的低功耗宽范围三段式TDC电路设计
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摘要
传统的多段式TDC电路结构随着分辨率精度的提高变得十分复杂,在阵列结构中的应用受到限制。电路设计在传统两段式TDC电路结构基础上,将高段位进行二次拆分,通过计数锁存/传输电路复用的结构,完成一种低功耗宽范围的时间数字转换。同时简化电路和缩小面积,使其可以应用于大阵列系统中。该时间数字转换电路在TSMC 0.35μm工艺、3.3 V电源电压条件下进行了仿真验证。在输入环振时钟为143.4 MHz条件下,可达到分辨率精度0.87 ns,测试量程3.63μs,功耗约1.88 mW。
The traditional multi-segment TDC circuit structure becomes very complex with the improvement of resolution accuracy, and its application in array structure is limited. Based on the traditional two-stage TDC circuit structure, the circuit design in this paper divides the high segment into two parts, and completes a time-to-digital conversion with low power consumption and wide range by counting latch/transmission circuit multiplexing structure. It simplifies the circuit and reduces the area so that it can be applied to large array systems. The time-to-digital conversion circuit is simulated and verified under TSMC 0.35 um process and 3.3 V power supply voltage. When the input ring oscillator clock is 143.4 MHz, the resolution accuracy is 0.87 ns, the measurement range is 3.63 μs, and the power consumption is about 1.88 mW.
The traditional multi-segment TDC circuit structure becomes very complex with the improvement of resolution accuracy, and its application in array structure is limited. Based on the traditional two-stage TDC circuit structure, the circuit design in this paper divides the high segment into two parts, and completes a time-to-digital conversion with low power consumption and wide range by counting latch/transmission circuit multiplexing structure. It simplifies the circuit and reduces the area so that it can be applied to large array systems. The time-to-digital conversion circuit is simulated and verified under TSMC 0.35 um process and 3.3 V power supply voltage. When the input ring oscillator clock is 143.4 MHz, the resolution accuracy is 0.87 ns, the measurement range is 3.63 μs, and the power consumption is about 1.88 mW.
引文
[1]夏婷婷,贺雅娟,甄少伟,甘武兵.一种自校准全数字TDC的设计[J].微电子学,2014,44(05):597-600.
[2]罗敏,宫月红,喻明艳.时间-数字转换器研究综述[J].微电子学,2014,44(03):372-376.
[3]宗士新.高分辨率数字时间转换器的设计[D].黑龙江:哈尔滨工业大学,2012.
[4]Roberts G W,Ali-Bakhshian M.A brief introduction to time-to-digital and digital-to-time converters[J].Circuits and SystemsⅡExpress Briefs IEEETransactions on,2010,57(3):153-157.
[5]B.Markovic,S.Tisa,A.Tosi,et al.A highlinearity,17ps precision time-to-digital converter based on a single-stage vernier dealy loop fine interpolation[J].IEEETransactions on Circuits and Systems,2013,60(3):557-569.
[6]Katoh K,Doi Y,Ito S,et al.An analysis of stochastic self-calibration of TDC using two ring oscillators[J].Proceedings of the Asian Test Symposium,2013,19(10):140-146.
[7]CHENG K H,HU C C,LIU J C,et al.A timeto-digital converter using multiphase-sampling and time amplifier for all digital phase-locked loop[A].IEEEInternational Symposium on Design and Diagnostics of Electronic Circuits and Systems(DDECS)[C].Vienna,2010:285-288.
[8]CHEN C C,CHANG W,CHEN P.A precise cyclic CMOS time-to-digital converter with low thermal sensitivity[J].IEEE Transactions on Nuclear Science,2004,3(4):1364-1367.
[9]CHEN W,Papavassiliou C.A low power 10-bit time-to-digital converter utilizing vernier delay lines[C].International Conference on Computer Modeling and Simulation,Uksim,2013:774-779.
[2]罗敏,宫月红,喻明艳.时间-数字转换器研究综述[J].微电子学,2014,44(03):372-376.
[3]宗士新.高分辨率数字时间转换器的设计[D].黑龙江:哈尔滨工业大学,2012.
[4]Roberts G W,Ali-Bakhshian M.A brief introduction to time-to-digital and digital-to-time converters[J].Circuits and SystemsⅡExpress Briefs IEEETransactions on,2010,57(3):153-157.
[5]B.Markovic,S.Tisa,A.Tosi,et al.A highlinearity,17ps precision time-to-digital converter based on a single-stage vernier dealy loop fine interpolation[J].IEEETransactions on Circuits and Systems,2013,60(3):557-569.
[6]Katoh K,Doi Y,Ito S,et al.An analysis of stochastic self-calibration of TDC using two ring oscillators[J].Proceedings of the Asian Test Symposium,2013,19(10):140-146.
[7]CHENG K H,HU C C,LIU J C,et al.A timeto-digital converter using multiphase-sampling and time amplifier for all digital phase-locked loop[A].IEEEInternational Symposium on Design and Diagnostics of Electronic Circuits and Systems(DDECS)[C].Vienna,2010:285-288.
[8]CHEN C C,CHANG W,CHEN P.A precise cyclic CMOS time-to-digital converter with low thermal sensitivity[J].IEEE Transactions on Nuclear Science,2004,3(4):1364-1367.
[9]CHEN W,Papavassiliou C.A low power 10-bit time-to-digital converter utilizing vernier delay lines[C].International Conference on Computer Modeling and Simulation,Uksim,2013:774-779.