基于FPGA的期货行情数据并行处理设计
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摘要
为解决期货行情数据处理中,基于软件的传统处理方式带来的处理时间长、延迟高、处理速率低的问题,提出并实现一种基于FPGA的非阻塞并行计算处理设计,完成对行情数据的加速还原计算功能。通过测试对比分析,该设计每秒可完成45万笔消息的处理,相比于软件的处理方式,处理速率提高了70%,极大程度缩短了行情消息的计算处理延迟,降低了时间开销,增加了系统处理效率,在低延迟期货交易系统设计和行情数据加速处理应用中具有较高实用价值。
To solve the problem of long processing time,high delay and low processing rate brought by the traditional software processing method in the processing of futures market data,the design of non blocking parallel computing processing based on FPGA was advanced and implemented,and the function of acceleration reduction calculation of the market data was completed.Through the test and comparison analysis,450 thousand messages per second were processed.Compared with the way of software processing,the processing speed is increased by 70%.The delay of computing and processing the market messages were shortened greatly,the time cost is reduced,and the efficiency of the system processing is increased.The proposed method is practical in the application of designing low delay futures trading system and accelerating processing.
To solve the problem of long processing time,high delay and low processing rate brought by the traditional software processing method in the processing of futures market data,the design of non blocking parallel computing processing based on FPGA was advanced and implemented,and the function of acceleration reduction calculation of the market data was completed.Through the test and comparison analysis,450 thousand messages per second were processed.Compared with the way of software processing,the processing speed is increased by 70%.The delay of computing and processing the market messages were shortened greatly,the time cost is reduced,and the efficiency of the system processing is increased.The proposed method is practical in the application of designing low delay futures trading system and accelerating processing.
引文
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[16]Zhang Pei,Aaron Mills,Joseph Zambreno,et al.The design and integration of a software configurable and parallelized coprocessor architecture for LQR control[J].Journal of Parallel and Distributed Computing,2017,35(17):87-91.
[2]HUANG Qiubo,CHEN Zhi,SU Houqin.Design and implementation of management and service module for complex transaction processing strategy in securities trading[J].Computer Application and Software,2015,32(4):91-94(in Chinese).[黄秋波,陈智,苏厚勤.证券交易复杂事件处理策略管理服务模块的设计与实现[J].计算机应用与软件,2015,32(4):91-94.]
[3]DU Xiaofu.Design of futures trading system based on data and transaction independence[J].New Communication in China,2017,19(14):160-161(in Chinese).[杜小甫.数据与交易独立的期货程序化交易系统设计[J].中国新通信,2017,19(14):160-161.]
[4]ZHANG Peng.Analysis and design of futures electronic trading platform[J].Information System Engineering,2016,44(2):14-15(in Chinese).[张鹏.期货电子化交易平台的分析与设计[J].信息系统工程,2016,44(2):14-15.]
[5]XU Chuanpei,QIU Pingting,WAN Chunting.Research on parallel test of network routers based on FPGA[J].Microellectronics and Computer,2015,32(12):163-168(in Chinese).[许川佩,邱凭婷,万春霆.基于FPGA的片上网络路由器并行测试研究[J].微电子学与计算机,2015,32(12):163-168.]
[6]WANG Huan,ZHANG Yuqing,CHEN Shuanggang,et al.Design of laboratory video monitoring system based on ARMplatform[J].Computer Engineering and Design,2018,39(5):56-59(in Chinese).[王欢,张玉清,陈双刚,等.基于ARM平台的实验室视频监控系统设计[J].计算机工程与设计,2018,39(5):56-59.]
[7]Wang Qian,Li Youjie,Shao Botang.Energy efficient parallel neuromorphic architectures with approximate arithmetic on FP-GA[J].Neurocomputing,2017,12(15):76-80.
[8]Liu Chen,Ma Rui,Bai Hao,et al.A new approach for FP-GA-based real-time simulation of power electronic system with no simulation latency in subsystem partitioning[J].International Journal of Electrical Power and Energy Systems,2018,19(31):23-27.
[9]WU Liangjing,CAO Yunfeng,DING Meng,et al.Visual algorithm acceleration system design of SoC FPGA[J].Application of Single Chip Computer and Embedded System,2016,16(11):58-62(in Chinese).[吴良晶,曹云峰,丁萌,等.SoC FPGA的视觉算法加速系统设计[J].单片机与嵌入式系统应用,2016,16(11):58-62.]
[10]YAN Zhe,ZHANG Li,ZHANG Xiangnan,et al.ARM dynamic startup loading technology based on FPGA control[J].Computer Engineering and Design,2018,39(4):60-63(in Chinese).[闫哲,张力,张翔南,等.基于FPGA控制的ARM动态启动加载技术[J].计算机工程与设计,2018,39(4):60-63.]
[11]WANG Zhongjie.Development of intelligent video surveillance system for labs[J].Techniques of Automation and Applications,2016,35(5):115-177(in Chinese).[王中杰.实验室智能视频监控系统开发[J].自动化技术与应用,2016,35(5):115-177.]
[12]ZHANG Jian.Design of Speedcore acceleration SoC for embedded FPGA IP product[J].Integrated Circuit Application,2017,17(8):34-37(in Chinese).[张健.嵌入式FPGAIP产品Speedcore加速SoC设计[J].集成电路应用,2017,17(8):34-37.]
[13]Xu Jinwei,Liu Zhiqiang,Jiang Jingfei,et al.High performance robust audio event recognition system based on FPGAplatform[J].Cognitive Systems Research,2018,12(34):70-75.
[14]TANG Rui,YE Liping,WANG Jingkun,et al.Design and implementation of double read and write channel on DDR3[J].Automatic Instrument,2018,39(4):14-17(in Chinese).[唐瑞,叶李萍,王经坤,等.DDR3上的双读写通道设计与实现[J].自动化仪表,2018,39(4):14-17.]
[15]DING Peipei,ZHENG Lie,LI Hong.Design and implementation of DDR3SDRAM controller based on FPGA[J].Information Recording Material,2018,19(5):64-66(in Chinese).[丁培培,郑列,李宏.基于FPGA的DDR3SDRAM控制器设计与实现方法[J].信息记录材料,2018,19(5):64-66.]
[16]Zhang Pei,Aaron Mills,Joseph Zambreno,et al.The design and integration of a software configurable and parallelized coprocessor architecture for LQR control[J].Journal of Parallel and Distributed Computing,2017,35(17):87-91.