一种新型隧穿场效应晶体管
|
摘要
提出了一种新型隧穿场效应晶体管(TFET)结构,该结构通过在常规TFET靠近器件栅氧化层一侧的漏-体结界面引入一薄层二氧化硅(隔离区),从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿(BTBT),减弱TFET的双极效应,实现大幅度降低器件泄漏电流的目的。利用TCAD仿真工具对基于部分耗尽绝缘体上硅(PDSOI)和全耗尽绝缘体上硅(FDSOI)的TFET和新型TFET结构进行了仿真与对比。仿真结果表明,当隔离区宽度为2 nm,高度大于10 nm时,可阻断PDSOI TFET的BTBT,其泄漏电流下降了4个数量级;而基于FDSOI的TFET无法彻底消除BTBT和双极效应,其泄漏电流下降了2个数量级。因此新型结构更适合于PDSOI TFET。
A new structure of tunneling-FET(TFET) was proposed. A thin layer of SiO_2 was inser-ted into the interface of the junction of drain and bulk near the gate-oxide side of the traditional TFET to eliminate or even to block band to band tunneling(BTBT) under a reverse gate bias condition, the bipolar effect of the TFET was decreased, and the leakage current was reduced greatly. The structures of the traditional TFET and the new TFET based on partially depleted silicon-on-insulator(PDSOI) and fully depleted silicon-on-insulator(FDSOI) were simulated and compared with TCAD simulation tools. The simulation results show that the BTBT of the PDSOI TFET can be blocked when the isolation region is 2 nm wide and the height is greater than 10 nm, and the leakage current is reduced by 4 orders of magnitude; the BTBT and bipolar effects of the FDSOI TFET cannot be eliminated completely, and the leakage current is reduced by 2 orders of magnitude. Therefore, the new structure is more suitable for the PDSOI TFET.
A new structure of tunneling-FET(TFET) was proposed. A thin layer of SiO_2 was inser-ted into the interface of the junction of drain and bulk near the gate-oxide side of the traditional TFET to eliminate or even to block band to band tunneling(BTBT) under a reverse gate bias condition, the bipolar effect of the TFET was decreased, and the leakage current was reduced greatly. The structures of the traditional TFET and the new TFET based on partially depleted silicon-on-insulator(PDSOI) and fully depleted silicon-on-insulator(FDSOI) were simulated and compared with TCAD simulation tools. The simulation results show that the BTBT of the PDSOI TFET can be blocked when the isolation region is 2 nm wide and the height is greater than 10 nm, and the leakage current is reduced by 4 orders of magnitude; the BTBT and bipolar effects of the FDSOI TFET cannot be eliminated completely, and the leakage current is reduced by 2 orders of magnitude. Therefore, the new structure is more suitable for the PDSOI TFET.
引文
[1] 黄如,黎明,安霞,等.后摩尔时代集成电路的新器件技术[J].中国科学:信息科学, 2012, 42(12):1529-1543.HUANG R,LI M,AN X, et al. New device technologies of integrated circuit in post-Moore era [J]. Scientia Sinica (Informationis), 2012, 42(12): 1529-1543 (in Chinese).
[2] SHARMA A, GOUD A A, ROY K, et al. GaSb-InAs n-TFET with doped source underlap exhibiting low subthreshold swing at sub-10-nm gate-lengths[J]. IEEE Electron Device Letters, 2014,35(12):1221-1223.
[3] SEABAUGH A C, ZHANG Q. Low-voltage tunnel transistors for beyond CMOS logic[J]. Proceedings of the IEEE, 2010, 98(12): 2095-2110.
[4] CHOI K M, CHOI W Y. Work-function variation effects of tunneling field-effect transistors (TFETs) [J]. IEEE Electron Device Letters, 2013, 34(8): 942-944.
[5] HUANG P C, TANAMOTO T, GOTO M, et al. Investigation of electrical characteristics of vertical junction Si n-type tunnel FET[J]. IEEE Transactions on Electron Devices,2018, 65 (12): 5511-5517.
[6] HUANG Q Q, ZHAN Z, HUANG R, et al. Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold slope and high ION/IOFF by gate configuration and barrier modulation[C]//Proceedings of International Electron Devices Meeting. Washington, DC, USA, 2011: 382-385.
[7] HUANG Q Q, HUANG R, ZHAN Z, et al. Performance improvement of Si pocket-tunnel FET with steep subthreshold slope and high ION/IOFF ratio[C]//Proceedings of the 11th International Conference on Solid-State and Integrated Circuit Technology. Xi′an, China, 2012: 1-3.
[8] LU H, ESSENI D, SEABAUGH A. Universal analytic model for tunnel FET circuit simulation [J]. Solid-State Electronics, 2015, 108: 110-117.
[2] SHARMA A, GOUD A A, ROY K, et al. GaSb-InAs n-TFET with doped source underlap exhibiting low subthreshold swing at sub-10-nm gate-lengths[J]. IEEE Electron Device Letters, 2014,35(12):1221-1223.
[3] SEABAUGH A C, ZHANG Q. Low-voltage tunnel transistors for beyond CMOS logic[J]. Proceedings of the IEEE, 2010, 98(12): 2095-2110.
[4] CHOI K M, CHOI W Y. Work-function variation effects of tunneling field-effect transistors (TFETs) [J]. IEEE Electron Device Letters, 2013, 34(8): 942-944.
[5] HUANG P C, TANAMOTO T, GOTO M, et al. Investigation of electrical characteristics of vertical junction Si n-type tunnel FET[J]. IEEE Transactions on Electron Devices,2018, 65 (12): 5511-5517.
[6] HUANG Q Q, ZHAN Z, HUANG R, et al. Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold slope and high ION/IOFF by gate configuration and barrier modulation[C]//Proceedings of International Electron Devices Meeting. Washington, DC, USA, 2011: 382-385.
[7] HUANG Q Q, HUANG R, ZHAN Z, et al. Performance improvement of Si pocket-tunnel FET with steep subthreshold slope and high ION/IOFF ratio[C]//Proceedings of the 11th International Conference on Solid-State and Integrated Circuit Technology. Xi′an, China, 2012: 1-3.
[8] LU H, ESSENI D, SEABAUGH A. Universal analytic model for tunnel FET circuit simulation [J]. Solid-State Electronics, 2015, 108: 110-117.