基于Bus-Invert编码的低功耗AES加密电路设计
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摘要
随着无线设备的广泛应用,半导体应用市场对低功耗加密电路提出了更高的要求.降低功耗可以延长无线设备的工作时间以及待机时间,而加密电路能够保障数据传输的安全性.在低功耗设计方法中,通过对信号编码来降低信号翻转率具有重要的研究意义.BI(Bus-Invert)编码技术可以降低随机信号的翻转率,在AES加密电路中引入BI编码技术,对电路输入数据BI编码,可得到一种改进型的低功耗AES加密电路.经验证,与原电路相比,改进型电路的ShiftRow、MixColumn、SubByte、KeyExpansion各子模块每周期内的平均翻转率分别降低了68%、42%、50%、46%,动态功耗降低了36.4%.
With the widespread use of wireless devices,the semiconductor application market has placed higher demands on low-power encryption circuits.Reducing power consumption can extend the operating time and standby time of wireless devices,while encryption circuits ensure data transmission security.In the low-power design method,it is of great research significance to reduce the signal toggle rate by coding the signal.BI(Bus-Invert)[1]coding technology can reduce the toggle rate of random signals.By introducing BI coding technology in AES encryption circuit and encoding input data,an improved low-power AES encryption circuit can be obtained.It is verified that compared with the original circuit,the average toggle rate of the ShiftRow,MixColumn,SubByte,and KeyExpansion sub-modules of the improved circuit is reduced by 68%,42%,50%,and 46%,respectively,and the dynamic power consumption is reduced 36.4%.
With the widespread use of wireless devices,the semiconductor application market has placed higher demands on low-power encryption circuits.Reducing power consumption can extend the operating time and standby time of wireless devices,while encryption circuits ensure data transmission security.In the low-power design method,it is of great research significance to reduce the signal toggle rate by coding the signal.BI(Bus-Invert)[1]coding technology can reduce the toggle rate of random signals.By introducing BI coding technology in AES encryption circuit and encoding input data,an improved low-power AES encryption circuit can be obtained.It is verified that compared with the original circuit,the average toggle rate of the ShiftRow,MixColumn,SubByte,and KeyExpansion sub-modules of the improved circuit is reduced by 68%,42%,50%,and 46%,respectively,and the dynamic power consumption is reduced 36.4%.
引文
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[2]NIST.FIPS PUBS 197.Advanced Encryption Standard(AES)[S].America:National Institute of Standards and Technology,2001.
[3]BERTONI G,MACCHETTI M,NEGRI L,et al.Power-efficient ASIC synthesis of cryptographic sboxes[C]//Acm Great Lakes Symposium on VLSI.Boston:ACM,2004:277-281.
[4]ZHANG J Y,ZUO Q H,ZHANG T B.Reducing the power consumption of the AES S-Box by SSC[C]//International Conference on Wireless Communications,Networking and Mobile Computing.Shanghai:IEEE,2007:2226-2229.
[5]MEHTA H,OWENS R M,IRWIN M J.Some issues in gray code addressing[C]//Proceedings of the Sixth Great Lakes Symposium on VLSI.Ames:IEEE,1996:178-181.
[6]GOLSON S.One-hot state machine design for FPGAs[C]//Proc.3rdAnnual PLD Design Conference&Exhibit,1993:1.1.3.B.
[7]CHOI H S,CHOI J H,KIM J T.Low-Power AESdesign using parallel architecture[C]//2008International Conference on Convergence&Hybrid Information Technology.Daejeon:IEEE,2008:413-416.
[8]HESHAM S,ABD EL GHANY M A,HOFMANNK.High throughput architecture for the advanced encryption standard algorithm[C]//17th International Symposium on Design&Diagnostics of Electronic Circuits&Systems.Warsaw:IEEE,2014:167-170.
[9]BUI D H,PUSCHINI D,BACLES-MIN S,et al.Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications[C]//2016International Conference on IC Design and Technology(ICICDT).Ho Chi Minh City:IEEE,2016:1-4.
[10]HAGHIGHIZADEH F,ATTARZADEH H,SHAR-IFKHANI M.A compact 8-Bit AES crypto-processor[C]//2010Second International Conference on Computer&Network Technology.Bangkok:IEEE,2010:71-75.