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一种毫米波瓦式T/R组件专用芯片架构
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  • 英文篇名:A Special Chip Topology Used in Tile T/R Module for Millimeter Wave Applications
  • 作者:张凯
  • 英文作者:ZHANG Kai;The 10th Institute of China Electronics Technology Group Corporation;
  • 关键词:毫米波 ; 瓦式 ; T/R组件 ; 芯片架构
  • 英文关键词:millimeter wave;;tile;;T/R module;;chip topology
  • 中文刊名:WBXB
  • 英文刊名:Journal of Microwaves
  • 机构:中国电子科技集团公司第十研究所;
  • 出版日期:2019-06-26 16:47
  • 出版单位:微波学报
  • 年:2019
  • 期:v.35
  • 语种:中文;
  • 页:WBXB201903018
  • 页数:4
  • CN:03
  • ISSN:32-1493/TN
  • 分类号:84-87
摘要
毫米波有源相控阵瓦式T/R组件工作频率高、波长短、单通道布局空间小,对T/R组件芯片级和子阵级集成设计提出不小挑战。相比而言,芯片级一次集成在提高集成密度、降低组件成本方面具有明显优势。文中根据瓦式T/R组件的布局特点,在芯片级集成层面,提出一种可灵活扩展、兼顾不同半导体工艺优势、功能划分合理的专用芯片集成架构。该架构在满足链路指标的前提下,可实现单通道芯片数量占比3/4只、面积占用不到3.7mm~2,显著提高了芯片级集成密度和功能密度,降低了T/R组件单通道实现成本,适用于毫米波频段任意规模的相控阵天线的高效扩展集成。
        The tile T/R module for millimeter wave active electronically scanned array(AESA) has the characteristics of higher frequency, shorter wave-length and narrower space between two adjacent channels, and is facing the challenges of chip-level and sub-array-level integrating designs. Chip-level integration has obvious advantages for enhancing integrated density and reducing cost. According to the tile module's characteristics, a special chip topology is proposed, which has notable values such as flexible extending ability, compatibility for different semiconductor technology, and reasonable configuration for T/R chain's functions. By using this topology, a single T/R channel can be realized only by 3/4 chip and area under 3.7 mm~2. This is very useful for reducing cost and assembling difficulty, and can be applied in extending integrations for millimeter wave AESA.
引文
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