一种低压低功耗高精度Σ-Δ调制器
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摘要
设计了一种应用于智能传感器的3阶3位量化离散时间Σ-Δ调制器。采用低失真的CIFF前馈结构,降低了对运算放大器输出摆幅的要求。基于改进的Class AB结构的电流镜跨导运算放大器(OTA),提出了带电容增益复位的有源加法器,降低了加法器中OTA对压摆率的要求,减小了调制器的功耗。采用TSMC 0.18μm 1P4M CMOS工艺进行设计与仿真。结果表明,在1 V电源电压下,能够实现有效位数大于16位的高精度,无杂散动态范围(SFDR)达到105 dB,调制器的整体功耗为340μW。
A 3-order, 3-bit quantization and discrete-time Σ-Δ modulator for smart sensors was designed. The low distortion CIFF feedforward structure was used to reduce the output swing of the opamp. Based on the improved current mirror operational transconductance amplifier(OTA) with a Class AB structure, an active adder circuit with capacitance-reset gain was proposed, which decreased the OTA's slew rate requirement in the adder circuit and reduced the power consumption of the modulator. The modulator circuit was designed and simulated in TSMC 0.18 μm 1 P4 M process. The simulation results showed that a high resolution of 16-bit was implemented under the 1 V power supply voltage. The spurious-free dynamic range(SFDR) reached 105 dB, and the overall power consumption was 340 μW.
A 3-order, 3-bit quantization and discrete-time Σ-Δ modulator for smart sensors was designed. The low distortion CIFF feedforward structure was used to reduce the output swing of the opamp. Based on the improved current mirror operational transconductance amplifier(OTA) with a Class AB structure, an active adder circuit with capacitance-reset gain was proposed, which decreased the OTA's slew rate requirement in the adder circuit and reduced the power consumption of the modulator. The modulator circuit was designed and simulated in TSMC 0.18 μm 1 P4 M process. The simulation results showed that a high resolution of 16-bit was implemented under the 1 V power supply voltage. The spurious-free dynamic range(SFDR) reached 105 dB, and the overall power consumption was 340 μW.
引文
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[2] YAO L B,STEYAERT M S J,SANSEN W.A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS [J].IEEE J Sol Sta Circ,2004,39(11):1809-1818.
[3] SCHERIER R,THEMES G C.Understanding delta-sigma data converters [M].Piscataway:IEEE Press,2005.
[4] BAIRD R T,FIEZ T S.Improved ΔΣ DAC linearity using data weighted averaging [C] // Proceed Int Symp Circ & Syst.Seattle,WA,USA.1995,1:13-16.
[5] SCHERIER R,SILVA J,STEENSSGAARD J,et al.Design-oriented estimation of thermal noise in switched-capacitor circuits [J].IEEE Trans Circ & Syst I:Regu Pap,2005,52(11):2358-2368.
[6] DESSOUKY M,KAISER A.Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping [J].IEEE J Sol Sta Circ,2001,36(3):349-355.
[7] ZHAO J C,ZHAO M L,WU X B,et al.A 0.9-V switched-opamp-based delta-sigma ADC with dual cycle shift DWA [J].J Semicond,2013,34(6):110-117.
[8] DE LA ROSA J M,SHERIER R,PUN K P,et al.Next-generation delta-sigma converters:trends and perspectives [J].IEEE J Emerg & Select Topics Circ & Syst,2015,5(4):484-499.
[9] BILLA S,SUKUMARAN A,PAVAN S.A 280 μW 24 kHz-BW 98.5 dB-SNDR chopped single-bit CT ΔΣM achieving <10 Hz 1/f noise corner without chopping artifacts [C] // IEEE Int Sol Sta Circ Conf.San Francisco,CA,USA.2016:276-277.
[10] SUKUMARAN A,PAVAN S.Low power design techniques for single-bit audio continuous-time delta sigma ADCs using FIR feedback [J].IEEE J Sol Sta Circ,2014,49(11):2515-2525.
[11] PARK H,NAM K Y,SU D K,et al.A 0.7-V 870-μW digital-audio CMOS sigma-delta modulator [J].IEEE J Sol Sta Circ,2009,44(4):1078-1088.