基于PUF的Logistic混沌序列发生器
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摘要
由于Logistic非线性混沌系统在一定的参数下,具有初值敏感性和拓扑复杂性等特点,因此Logistic混沌系统可以作为随机序列信号发生器。同时由于集成电路在生产、制作的过程中,即使采用完全相同的设计方法和制造工艺,也会在器件上产生不可控的微小差异,这些微小差异便成为集成电路不可克隆的基础。基于此特点,提出了一种基于可编程逻辑阵列(FPGA)的双输出查找表(LUT)结构的物理不可克隆函数(PUF)的Logistic随机混沌序列信号发生器,该混沌序列发生器具有物理的唯一性,能够有效地抵抗对于系统的复制和攻击。将该系统在Xilinx公司的FPGA开发板上进行测试和验证,结果表明,同样的电路结构和配置文件在不同的FPGA开发板上能够产生不同的随机序列,提高了混沌序列的随机性。
Logistic nonlinear chaotic system has many good characters such as initial value sensitivity and topological mixing in the some parameter condition, which is used to create the random sequence signal generator. Because of the attributions of randomness and uniqueness even under the exact, the same circuit layouts and manufacturing procedures,there is still an instinct unclonable difference in each integrated circuit. Therefore, a new sequence stream generator was proposed based on Logistic chaotic system and physical unclonable function designed by double output look-up-table(LUT). The output of the Logistic sequence generator was associated with a specific physical circuit. This kind of sequence generator could resist an attack such as the replication of the keys of the system. The system was designed and tested on the Xilinx FPGA board. The results show that the same architecture of the circuit and the same config file operated on the different FPGA developing board can generate the total different random chaotic sequence stream and improve the randomness of the stream.
Logistic nonlinear chaotic system has many good characters such as initial value sensitivity and topological mixing in the some parameter condition, which is used to create the random sequence signal generator. Because of the attributions of randomness and uniqueness even under the exact, the same circuit layouts and manufacturing procedures,there is still an instinct unclonable difference in each integrated circuit. Therefore, a new sequence stream generator was proposed based on Logistic chaotic system and physical unclonable function designed by double output look-up-table(LUT). The output of the Logistic sequence generator was associated with a specific physical circuit. This kind of sequence generator could resist an attack such as the replication of the keys of the system. The system was designed and tested on the Xilinx FPGA board. The results show that the same architecture of the circuit and the same config file operated on the different FPGA developing board can generate the total different random chaotic sequence stream and improve the randomness of the stream.
引文
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[2]KANSO A,SMAOUI N.Logistic chaotic maps for binary numbers generations[J].Chaos Solitons&Fractals,2009,40(5):2557-2568.
[3]蔡丹,季晓勇,史贺,等.改进分段Logistic混沌映射的方法及其性能分析[J].南京大学学报(自然科学),2016,52(5):809-815.CAI D,JI X Y,SHI H,et al.Method for improving piecewise Logistic chaotic map and its performance analysis[J].Journal of Nanjing University,2016,52(5):809-815.
[4]XU L,LI Z,LI J,et al.A novel bit-level image encryption algorithm based on chaotic maps[J].Optics&Lasers in Engineering,2016,78(21):17-25.
[5]宣蕾,闫纪宁.基于混沌的“一组一密”分组密码[J].通信学报,2009,30(Z2):105-110.XUN L,YAN J N.The“one group one cipher”cryptograph of block cipher based on chaotic[J].Journal on Communications,2009,30(Z2):105-110.
[6]王俊,刘树波,梁才,等.基于PUF和IPI的可穿戴设备双因子认证协议[J].通信学报,2017,38(6):127-135.WANG J,LIU S B,LIANG C,et al.Two-factor wearable device authentication protocol based on PUF and IPI[J].Journal on Communications,2017,38(6):127-135.
[7]郭渊博,张紫楠,杨奎武.基于PUFS的不经意传输协议[J].通信学报,2013,34(Z1):38-43.GUO Y B,ZHANG Z N,YANG K W.Oblivious transfer based on physical unclonable function system[J].Journal on Communications,2013,34(Z1):38-43.
[8]DABAL P,PELKA R.FPGA implementation of chaotic pseudo-random bit generators[C]//Mixed Design of Integrated Circuits and Systems.2012:260-264.
[9]WANG H J,SONG B,LIU Q,et al.FPGA design and applicable analysis of discrete chaotic maps[J].International Journal of Bifurcation&Chaos,2014,24(4):917-921.
[10]ADAMO O,MOHANTYZ S P,KOIUGIANOS E,et al.VLSI architecture and FPGA prototyping of a digital camera for image security and authentication[C]//Region 5 Conference.2006:154-158.
[11]WANG Y,RENFA L I.FPGA based unified architecture for public key and private key cryptosystems[J].Frontiers of Computer Science,2013,7(3):307-316.
[12]GUAJARDO J,KUMAR S S,SCHRIJEN G J,et al.FPGA intrinsic PUFs and their use for IP protection[C]//International Workshop on Cryptographic Hardware and Embedded Systems.2007:63-80.
[13]TUNCER T.The implementation of chaos-based PUF designs in field programmable gate array[J].nonlinear dynamics,2016,86(2):1-12.
[14]LIU L,HUANG H,HU S.Lorenz chaotic system based carbon nanotube physical unclonable functions[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2017,PP(99):1.
[15]KUMAR S.The buttefly PUF:protecting IP on every FPGA[C]//IEEEInternational Workshop on Hardware Oriented Security and Trust.2008.
[16]庞子涵,周强,高文超,等.高效能FPGA毛刺PUF设计与实现[J].计算机辅助设计与图形学学报,2017,29(6):1135-1144.PANG Z H,ZHOU Q,GAO W C,et al.Design and implementation of high efficiency PUF circuit on FPGA[J].Journal of Computer-Aided Design&Computer Graphics,2017,29(6):1135-1144.
[17]CHENG H,SONG Y,HUANG C,et al.Self-adaptive chaotic Logistic map:an efficient image encryption method[J].Journal of Internet Technology,2016,17(4):743-752.