高速接口JESD204B的灵敏放大器设计
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摘要
采用UMC 28 nm CMOS工艺,在低电源电压下设计实现了一种高速、低失调的灵敏放大器。在传统差分放大器、AB类锁存器等电路的基础上进行改进,提出了一种新型结构的灵敏放大器。利用Cadence软件进行电路设计和功能仿真。仿真结果表明,所设计的电路在1.05 V的低电源电压、5/10 GHz时钟下,其失调电压分别为0.2 mV/0.8 mV,传输延迟分别为50 ps/42 ps,功耗分别为0.37 mW/0.44 mW。因此,所设计的灵敏放大器适用于高速接口JESD204B模数转换模块。
This paper introduces a high-speed, low-offset sense amplifier with low supply voltage in UMC 28 nm CMOS process.The paper presents a novel structure of the sense amplifier which bases on the traditional differential amplifier, class AB latch and other circuits. It′ s designed and verified in Cadence. The simulation results show that the proposed design exhibits 0.2 mV/0. 8 mV offset voltage, 63 ps/44 ps delay, 0.37 mW/0.44 mW power dissipation respectively with 1.05 V supply voltage when the clock signal at the 5/10 GHz. Therefore, the proposed sense amplifier is satisfied for the analog-to-digital converter of high-speed interface JESD204B.
This paper introduces a high-speed, low-offset sense amplifier with low supply voltage in UMC 28 nm CMOS process.The paper presents a novel structure of the sense amplifier which bases on the traditional differential amplifier, class AB latch and other circuits. It′ s designed and verified in Cadence. The simulation results show that the proposed design exhibits 0.2 mV/0. 8 mV offset voltage, 63 ps/44 ps delay, 0.37 mW/0.44 mW power dissipation respectively with 1.05 V supply voltage when the clock signal at the 5/10 GHz. Therefore, the proposed sense amplifier is satisfied for the analog-to-digital converter of high-speed interface JESD204B.
引文
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[2]田啸,何燕冬.6.25 Gb/s串行数据接收器设计[J].微电子学与计算机,2017,34(7):119-122.
[3]SHAKIR T,RENNIE D,SACHDEV M.Integrated read assist-sense amplifier scheme for high performance embedded SRAMs[J].Midwest Symposium on Circuits&Systems,2010:137-140.
[4]张华.一种低压高速灵敏放大器电路的设计[J].固体电子学研究与进展,2015(1):94-99.
[5]宁源.2.5 Gbps高速VML接口电路的设计与研究[D].西安:西安电子科技大学,2015.
[6]朱婷,夏建新,蒋见花.高速低功耗电流型灵敏放大器的设计[J].现代电子技术,2011,34(2):157-160.
[7]RAZAVI B.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2003.
[8]PHILLIP E A,DOUGLAS R H.CMOS模拟集成电路设计(第2版)[M].北京:电子工业出版社,2007.
[9]SCHINKEL D,MENSINK E,et al.A double-tail latch-type voltage sense amplifier with 18 ps Setup+Hold time[C].Solid-State Circuits Conference,2007.ISSCC 2007.Digest of Technical Papers.IEEE International.IEEE,2007:314-605.
[10]秦睿.基于0.18μm CMOS工艺的比较器设计[D].哈尔滨:黑龙江大学,2014.
[11]韦雪明.高速SERDES接口芯片设计关键技术研究[D].成都:电子科技大学,2012.
[12]彭宣霖,李航标,陈剑洛,等.一种高速低功耗动态比较器设计[J].微电子学,2014,44(5):601-605.