面向片上网络的高性能路由器关键技术研究
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摘要
随着工艺尺寸比例缩小,未来单芯片上将会集成数百个处理器核心,全局互连线延迟相对于门延迟也越来越大。传统的基于总线、专用互连线、交叉开关等互连方式由于受到带宽、可扩展性、面积、全局互连线延迟等问题的挑战,无法满足片上互连的需求。片上网络由于其具有良好的扩展性、可以预测的互连线长度和延迟、较高的带宽、可重用性等优点逐渐成为非常有前景的片上互连结构。同时,应用程序对片上互连结构提出了低延迟、高吞吐率的要求。虽然网络已经在并行计算和互联网络等领域进行了深入广泛的研究。但是片上网络与之相比较具有以下不同:路由器的延迟成为网络延迟的主要构成部分;具有丰富的互连线资源;有限的存储资源;更加严峻的功耗和面积约束。这些不同点是NoC研究的立足点和出发点。因此,本课题的研究也是针对这些问题展开的,主要工作体现在以下五个方面。
1.自适应通道双缓冲CDB。通道双缓冲CDB(Channel Double Buffer)用来替代链路中的寄存器,实现链路流水化。CDB之间以及CDB与路由器之间的报片传输采用了ready-valid握手协议。链路采用了局部拥塞控制策略,当下游路由器的输入缓冲器无法接收报片时,链路中的CDB能够缓冲报片。这等效的增加了路由器输入缓冲器的容量。基于逻辑努力建立的延迟模型显示:关键路径延迟与物理链路宽度密切相关;寄存器开销是关键路径延迟的重要构成部分。基于CDB的链路流水线级数与互连线类型、互连线长度和时钟周期宽度密切相关。与插入简单寄存器实现链路流水化相比较,基于CDB的链路流水化将会增加流水线级数,但是流水线级数的增加并不明显。
2.基于CDB的动态缓冲分配的DVOQR。DVOQR(Dynamic Virtual Output Queue Router)通过虚拟输出队列技术,前瞻路由计算策略,动态缓冲分配和虚拟地址队列结构,从而实现UDB读操作,前瞻路由计算和交叉开关分配能够并行进行,进而能够将路由器流水线压缩到两个时钟周期。动态缓冲分配机制可以有效的利用片上有限的缓冲资源。在随机通讯模式下,与虚通道路由器相比较,在获得相同网络吞吐率下,DVOQR的缓冲容量是虚通道路由器的四分之一。基于逻辑努力建立的延迟模型显示:路由器的端口数量对关键路径延迟的影响更加明显。在4x4 Mesh网络中,随机通讯模式下,DVOQR的吞吐率相对于虫孔路由器和虚通道路由器分别增加了46.9%和28.5%。即使在相同输入加速比下,DVOQR的吞吐率比两倍于其输入缓冲器容量的虚通道路由器仍高1.9%,与四倍于其输入缓冲器容量的虚通道路由器相当。应用程序的模拟结果显示:DVOQ路由器、虫孔路由器和虚通道路由器的平均延迟相对于理想路由器分别增加了6.6%,50.9%和94.6%。
3.低面积开销的基于编码分配的无缓冲路由器BEA-BLESS。BEA-BLESS(Based on Encoding Allocation BufferLESS router)是一种无缓冲路由器,能够有效的减小NoC对芯片面积需求。FBEA-BLESS和PBEA-BLESS分别针对报片交换和报文交换进行优化。BEA-BLESS通过编码分配策略能够降低路由器的关键路径延迟,提高路由器的工作频率。FBEA-BLESS工作频率是B-BLESS的2倍;网络活锁可以通过GoSS(Go-Stop-Steer)策略来避免。PBEA-BLESS能够以较小的缓冲面积开销来消除接收端的重排序缓冲;改进的GoSS策略可以避免网络活锁和饿死。真实应用程序的模拟结果显示:在BEA-BLESS中,网络平均延迟相对于B-BLESS降低了29.4%;支持报文交换所需要的缓冲器的容量仅仅为重排序缓冲器容量的33.3%。
4.基于DVOQR的负载均衡的多播路由器。通过借鉴单播通讯下网络吞吐率模型建立的方法,本文建立了面向多播通讯的网络吞吐率模型;并且提出了两种负载平衡的多播路由算法BDOR (Balanced DOR)和MPDOR(Minimal Path DOR)。SM-DVOQR (Supporting Multicast DVOQR)和SMDL-DVOQR(Supporting Multicast Double Lane DVOQR)是基于DVOQR的两种能够高效的支持多播的路由器。SM-DVOQR能够支持XY多播路由算法和YX多播路由算法。单一的采用XY多播路由算法或者YX多播路由算法将会导致网络的X方向和Y方向上的通道负载不平衡。这种不平衡的特性将会随着网络规模的增加而增加。SMDL-DVOQR通过在两个lane上分别支持XY多播路由算法和YX多播路由算法来实现负载均衡的BDOR和MPDOR多播路由算法。模拟结果显示:在Mesh网络中,通过增加路由器的局部输出端口的数量,网络性能可以获得改善,局部端口数量的最优值是2;SMDL-DVOQR由于能够平衡网络负载,因此能够获得比SM-DVOQR更好的性能。
5.面向DVOQR的漏流功耗优化策略。基于RTL级的DVOQR的功耗分析显示:路由器中的存储单元是漏流功耗的主要消耗部件,占据了总漏流功耗的85%;在低的网络通讯量下,漏流功耗是路由器总功耗的重要构成部分。自适应缓冲管理策略和两项缓冲不关闭策略是两种路由器的漏流功耗优化策略。自适应缓冲管理策略能够有效的降低路由器的漏流功耗,但是在较低的网络注入率下,缓冲项的唤醒操作延迟将会附加到网络平均延迟。在唤醒延迟Twakeup=1时,提前唤醒技术能够完全隐藏唤醒延迟。而两项缓冲不关闭技术能够容忍更大的唤醒延迟。在低注入率下,两项缓冲不关闭技术下,路由器的漏流功耗节约率小于自适应缓冲管理策略。在中等、较高注入率下,这两种策略下的漏流功耗节约率几乎相等。
With the technology scaling down, hundreds of processor cores are integrated into a single chip and global wire delays are in fact increasing while gates delays are scaling down. The conventional interconnect architectures such as bus, ad-hoc wire and crossbar, limited to the bandwidth, scalability, area and global wire delay can not satisfy the requirement of on-chip interconnect. NoC (Networks on Chip) are becoming the promising interconnects for the better scalability, predicted wire length and delay, high bandwidth and reusability. Scientific and commercial applications need on chip interconnects with the low latency and high throughput. The network has been studied widely in the parallel computers and internet. There are some differences between the NoC and those two types network. Router latency is the main component of the network latency in the NoC; NoC has more rich wire resource and less buffer capacity; NoC faces the very tight power and area budgets. The research of the thesis is based on these differences and focused on the low latency router architecture, pipelined physical link, low area overhead router, multicast and the low power design of the routers.
The primary innovative works in this thesis are as follows:
1. Adaptive CDB (Channel Double Buffer). CDBs are used to replace the link register implement the pipelined physical link. The ready-valid handshake flow control is adopted between CDBs and routers. The link adopt the local congest control and CDBs in the link can buffer Flits when the buffer in the downstream does not receive a Flit. This is equivalent to increasing the capacity of input buffer in the router. The delay model of CDB built based on the theory of logical effort displays that the delay of critical path is sensitive to the link width and the register overhead is main component of the critical path. The pipeline depth based on CDBs is sensitive to the wire type, wire length and clock cycle. Compared to the method of implement link pipeline by inserting register, the increase of pipeline depth based on CDBs is not obvious.
2. DVOQR (Dynamic Virtual Output Queue Router) with dynamic buffer allocation based on CDB. The UDB (Unified Dynamic Buffer) read, routing computation and switch allocation can be perform parallel through VOQ (Virtual Output Queue), look-ahead routing computation strategy, dynamic buffer allocation and VOAQ(Virtual Output Address Queue), which can reduce the router pipeline to two stages. Dynamic buffer allocation strategy can efficiently use the limited on-chip buffer resources. DVOQR with buffer being one quarter of that in the virtual channel router has the same throughput with the virtual channel router in the random traffic. The delay model established based on the logical effort theory shows that the critical path delay is more sensitive to the number of ports. The synthetic workload simulation results display that throughput of DVOQR relative to wormhole router and virtual channel router is increased by 46.9% and 28.5% in the 4x4 Mesh network and random traffic; Throughput of DVOQR is still high 1.9% than that of virtual channel router with twice buffer capacity of DVQOR, and is almost the same with that of virtual channel router with four times buffer capacity of DVQOR under the same input speedup. Application workload simulation results show that the network average delay of DVOQR, wormhole router and virtual channel router relative to the ideal router is increased 6.6%, 50.9% and 94.6% respectively.
3. BEA-BLESS (Based on Encoding Allocation BufferLESS router) with low area overhead. BEA-BLESS does not has input buffer and can reduce NoC to the chip area requirement. FBEA-BLESS is the Flit-switch router and PBEA-BLESS is the packet-switch router. Based on encoding allocation strategy adopted by the BEA-BLESS can reduce the critical path of router and increase the router work frequency. The frequency of BEA-BLESS is 2 times of the B-BLESS (Base BufferLESS router). The livelock can be avoided by the GoSS(Go-Stop-Steer) strategy. PBEA-BLESS router can use a small capacity buffer to eliminate the reordering buffer in the receiving end. The livelock and starvation can be avoided by improved GoSS strategy. Application workload simulation results show that the network average delay of BEA-BLESS relative to the B-BLESS is reduced by 29.4% and the capacity of buffer to support packet switching is only 33.3% of the capacity of the reorder buffer.
4. Multicast router with load balance based on DVOQR. The network throughput model of multicast has been established, learning from the throughput model of unicast. BDOR (Balanced Dimension Order Routing algorithm) and MPDOR (Minimal Path Dimension Order Routing algorithm) proposed in the thesis are load balance routing algorithm. SM-DVOQR (Supporting Multicast DVOQR) and SMDL-DVOQR (Supporting Multicast Double Lane DVOQR) are based on DVOQR and can support multicast efficiently. SM-DVOQR is able to support XY/YX multicast routing algorithm. These two algorithms will result in the channel load imbalance between the X and Y directions. And the imbalance will increase with the network size increase. SMDL-DVOQR, which has two lane, is able to support BDOR and MPDOR multicast routing algorithms through one lane supporting XY multicast algorithm and the other lane supporting YX multicast algorithm. The simulation results under random multicast traffic display that the network performance will increase with the number of local output port, which is the optimal value of 2 and SMDL-DVOQR, which can balance the network load, can obtain the better network performance than SM-DVOQR.
5. Leakage power optimization strategies for DVOQR. Power analysis results of DVOQR based on RTL-level display that UDB and VOAQ are the main components consuming the leakage power and occupy the 85% of the total leakage power; and the leakage power is a important component of total power consumption under the low network traffic. Adaptive buffer management and two-entry-never-turned-off are the two leakage power optimization strategies. Adaptive buffer management strategy can effectively reduce leakage power consumption. But the buffer wakeup delay will be attached to the network average delay at a lower network injection rate. The look-ahead wake up technology can fully hide the wake up delay with Twakeup=1. While, Two-entry-never-turned-off strategy can tolerate a larger wake up delay. The leakage power savings rate of Two-entry-never-turned-off strategy is less than that of adaptive buffer management strategy under the low network injection rate. But the leakage power savings rate of two strategies is almost the same under the middle or high network injection rate.
1.自适应通道双缓冲CDB。通道双缓冲CDB(Channel Double Buffer)用来替代链路中的寄存器,实现链路流水化。CDB之间以及CDB与路由器之间的报片传输采用了ready-valid握手协议。链路采用了局部拥塞控制策略,当下游路由器的输入缓冲器无法接收报片时,链路中的CDB能够缓冲报片。这等效的增加了路由器输入缓冲器的容量。基于逻辑努力建立的延迟模型显示:关键路径延迟与物理链路宽度密切相关;寄存器开销是关键路径延迟的重要构成部分。基于CDB的链路流水线级数与互连线类型、互连线长度和时钟周期宽度密切相关。与插入简单寄存器实现链路流水化相比较,基于CDB的链路流水化将会增加流水线级数,但是流水线级数的增加并不明显。
2.基于CDB的动态缓冲分配的DVOQR。DVOQR(Dynamic Virtual Output Queue Router)通过虚拟输出队列技术,前瞻路由计算策略,动态缓冲分配和虚拟地址队列结构,从而实现UDB读操作,前瞻路由计算和交叉开关分配能够并行进行,进而能够将路由器流水线压缩到两个时钟周期。动态缓冲分配机制可以有效的利用片上有限的缓冲资源。在随机通讯模式下,与虚通道路由器相比较,在获得相同网络吞吐率下,DVOQR的缓冲容量是虚通道路由器的四分之一。基于逻辑努力建立的延迟模型显示:路由器的端口数量对关键路径延迟的影响更加明显。在4x4 Mesh网络中,随机通讯模式下,DVOQR的吞吐率相对于虫孔路由器和虚通道路由器分别增加了46.9%和28.5%。即使在相同输入加速比下,DVOQR的吞吐率比两倍于其输入缓冲器容量的虚通道路由器仍高1.9%,与四倍于其输入缓冲器容量的虚通道路由器相当。应用程序的模拟结果显示:DVOQ路由器、虫孔路由器和虚通道路由器的平均延迟相对于理想路由器分别增加了6.6%,50.9%和94.6%。
3.低面积开销的基于编码分配的无缓冲路由器BEA-BLESS。BEA-BLESS(Based on Encoding Allocation BufferLESS router)是一种无缓冲路由器,能够有效的减小NoC对芯片面积需求。FBEA-BLESS和PBEA-BLESS分别针对报片交换和报文交换进行优化。BEA-BLESS通过编码分配策略能够降低路由器的关键路径延迟,提高路由器的工作频率。FBEA-BLESS工作频率是B-BLESS的2倍;网络活锁可以通过GoSS(Go-Stop-Steer)策略来避免。PBEA-BLESS能够以较小的缓冲面积开销来消除接收端的重排序缓冲;改进的GoSS策略可以避免网络活锁和饿死。真实应用程序的模拟结果显示:在BEA-BLESS中,网络平均延迟相对于B-BLESS降低了29.4%;支持报文交换所需要的缓冲器的容量仅仅为重排序缓冲器容量的33.3%。
4.基于DVOQR的负载均衡的多播路由器。通过借鉴单播通讯下网络吞吐率模型建立的方法,本文建立了面向多播通讯的网络吞吐率模型;并且提出了两种负载平衡的多播路由算法BDOR (Balanced DOR)和MPDOR(Minimal Path DOR)。SM-DVOQR (Supporting Multicast DVOQR)和SMDL-DVOQR(Supporting Multicast Double Lane DVOQR)是基于DVOQR的两种能够高效的支持多播的路由器。SM-DVOQR能够支持XY多播路由算法和YX多播路由算法。单一的采用XY多播路由算法或者YX多播路由算法将会导致网络的X方向和Y方向上的通道负载不平衡。这种不平衡的特性将会随着网络规模的增加而增加。SMDL-DVOQR通过在两个lane上分别支持XY多播路由算法和YX多播路由算法来实现负载均衡的BDOR和MPDOR多播路由算法。模拟结果显示:在Mesh网络中,通过增加路由器的局部输出端口的数量,网络性能可以获得改善,局部端口数量的最优值是2;SMDL-DVOQR由于能够平衡网络负载,因此能够获得比SM-DVOQR更好的性能。
5.面向DVOQR的漏流功耗优化策略。基于RTL级的DVOQR的功耗分析显示:路由器中的存储单元是漏流功耗的主要消耗部件,占据了总漏流功耗的85%;在低的网络通讯量下,漏流功耗是路由器总功耗的重要构成部分。自适应缓冲管理策略和两项缓冲不关闭策略是两种路由器的漏流功耗优化策略。自适应缓冲管理策略能够有效的降低路由器的漏流功耗,但是在较低的网络注入率下,缓冲项的唤醒操作延迟将会附加到网络平均延迟。在唤醒延迟Twakeup=1时,提前唤醒技术能够完全隐藏唤醒延迟。而两项缓冲不关闭技术能够容忍更大的唤醒延迟。在低注入率下,两项缓冲不关闭技术下,路由器的漏流功耗节约率小于自适应缓冲管理策略。在中等、较高注入率下,这两种策略下的漏流功耗节约率几乎相等。
With the technology scaling down, hundreds of processor cores are integrated into a single chip and global wire delays are in fact increasing while gates delays are scaling down. The conventional interconnect architectures such as bus, ad-hoc wire and crossbar, limited to the bandwidth, scalability, area and global wire delay can not satisfy the requirement of on-chip interconnect. NoC (Networks on Chip) are becoming the promising interconnects for the better scalability, predicted wire length and delay, high bandwidth and reusability. Scientific and commercial applications need on chip interconnects with the low latency and high throughput. The network has been studied widely in the parallel computers and internet. There are some differences between the NoC and those two types network. Router latency is the main component of the network latency in the NoC; NoC has more rich wire resource and less buffer capacity; NoC faces the very tight power and area budgets. The research of the thesis is based on these differences and focused on the low latency router architecture, pipelined physical link, low area overhead router, multicast and the low power design of the routers.
The primary innovative works in this thesis are as follows:
1. Adaptive CDB (Channel Double Buffer). CDBs are used to replace the link register implement the pipelined physical link. The ready-valid handshake flow control is adopted between CDBs and routers. The link adopt the local congest control and CDBs in the link can buffer Flits when the buffer in the downstream does not receive a Flit. This is equivalent to increasing the capacity of input buffer in the router. The delay model of CDB built based on the theory of logical effort displays that the delay of critical path is sensitive to the link width and the register overhead is main component of the critical path. The pipeline depth based on CDBs is sensitive to the wire type, wire length and clock cycle. Compared to the method of implement link pipeline by inserting register, the increase of pipeline depth based on CDBs is not obvious.
2. DVOQR (Dynamic Virtual Output Queue Router) with dynamic buffer allocation based on CDB. The UDB (Unified Dynamic Buffer) read, routing computation and switch allocation can be perform parallel through VOQ (Virtual Output Queue), look-ahead routing computation strategy, dynamic buffer allocation and VOAQ(Virtual Output Address Queue), which can reduce the router pipeline to two stages. Dynamic buffer allocation strategy can efficiently use the limited on-chip buffer resources. DVOQR with buffer being one quarter of that in the virtual channel router has the same throughput with the virtual channel router in the random traffic. The delay model established based on the logical effort theory shows that the critical path delay is more sensitive to the number of ports. The synthetic workload simulation results display that throughput of DVOQR relative to wormhole router and virtual channel router is increased by 46.9% and 28.5% in the 4x4 Mesh network and random traffic; Throughput of DVOQR is still high 1.9% than that of virtual channel router with twice buffer capacity of DVQOR, and is almost the same with that of virtual channel router with four times buffer capacity of DVQOR under the same input speedup. Application workload simulation results show that the network average delay of DVOQR, wormhole router and virtual channel router relative to the ideal router is increased 6.6%, 50.9% and 94.6% respectively.
3. BEA-BLESS (Based on Encoding Allocation BufferLESS router) with low area overhead. BEA-BLESS does not has input buffer and can reduce NoC to the chip area requirement. FBEA-BLESS is the Flit-switch router and PBEA-BLESS is the packet-switch router. Based on encoding allocation strategy adopted by the BEA-BLESS can reduce the critical path of router and increase the router work frequency. The frequency of BEA-BLESS is 2 times of the B-BLESS (Base BufferLESS router). The livelock can be avoided by the GoSS(Go-Stop-Steer) strategy. PBEA-BLESS router can use a small capacity buffer to eliminate the reordering buffer in the receiving end. The livelock and starvation can be avoided by improved GoSS strategy. Application workload simulation results show that the network average delay of BEA-BLESS relative to the B-BLESS is reduced by 29.4% and the capacity of buffer to support packet switching is only 33.3% of the capacity of the reorder buffer.
4. Multicast router with load balance based on DVOQR. The network throughput model of multicast has been established, learning from the throughput model of unicast. BDOR (Balanced Dimension Order Routing algorithm) and MPDOR (Minimal Path Dimension Order Routing algorithm) proposed in the thesis are load balance routing algorithm. SM-DVOQR (Supporting Multicast DVOQR) and SMDL-DVOQR (Supporting Multicast Double Lane DVOQR) are based on DVOQR and can support multicast efficiently. SM-DVOQR is able to support XY/YX multicast routing algorithm. These two algorithms will result in the channel load imbalance between the X and Y directions. And the imbalance will increase with the network size increase. SMDL-DVOQR, which has two lane, is able to support BDOR and MPDOR multicast routing algorithms through one lane supporting XY multicast algorithm and the other lane supporting YX multicast algorithm. The simulation results under random multicast traffic display that the network performance will increase with the number of local output port, which is the optimal value of 2 and SMDL-DVOQR, which can balance the network load, can obtain the better network performance than SM-DVOQR.
5. Leakage power optimization strategies for DVOQR. Power analysis results of DVOQR based on RTL-level display that UDB and VOAQ are the main components consuming the leakage power and occupy the 85% of the total leakage power; and the leakage power is a important component of total power consumption under the low network traffic. Adaptive buffer management and two-entry-never-turned-off are the two leakage power optimization strategies. Adaptive buffer management strategy can effectively reduce leakage power consumption. But the buffer wakeup delay will be attached to the network average delay at a lower network injection rate. The look-ahead wake up technology can fully hide the wake up delay with Twakeup=1. While, Two-entry-never-turned-off strategy can tolerate a larger wake up delay. The leakage power savings rate of Two-entry-never-turned-off strategy is less than that of adaptive buffer management strategy under the low network injection rate. But the leakage power savings rate of two strategies is almost the same under the middle or high network injection rate.
引文
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