UWB无线通信中的信道编解码VLSI实现
摘要
超宽带(Ultra WideBand,UWB)技术是一种采用纳秒级脉冲信号宽度、占用GHz级信号频谱、发送功率极低、适用于短距离的无线通信技术,以高分辨率、高截获率、信息含量大和能探测隐蔽目标等优点而成为无线通信领域研究和相关产品开发的热点。由于超宽带信号发射功率低、传送信息量大,容易受到各种干扰,因此降低数据传输过程中的误码率,从而提高通信的抗干扰能力是一个关键问题,通常采用在无线通信的基带芯片中加入信道编码的方法来提高通信系统信息传输的可靠性。本论文研究了UWB无线通信系统采用的信息传输差错控制方案,根据其物理层标准要求,设计并采用VLSI技术实现了参数为(3,1,7)的卷积码和基于最大似然率的Viterbi译码算法。本论文的主要工作包括:
首先总结了超宽带无线通信的基本概念和国内外发展动态。针对超宽带信道的特点,确定了信道编解码方案,即卷积码和基于Viterbi算法的译码方案,并且分析了Viterbi译码器的纠错性能。
其次,参照基于OFDM调制的物理层协议标准,设计并实现了(3,1,7)卷积码编码电路和Viterbi译码器。在关键路径的优化上,使用并行方式和新型的4:2压缩阵列设计了高速并行ACS电路。电路使用Verilog HDL语言进行描述,Modelsim软件等进行功能仿真。编码器采用Math Works公司的Matlab软件平台进行建模,并产生测试所需要的软判决信息。最后使用EDA工具对设计进行逻辑级优化和VLSI实现。
最后,验证结果表明,在系统时钟132MHz情况下,电路功能正确,满足了规范中的时序要求。其中,关键路径中的ACS模块的最高工作频率比传统的串行结构ACS提高了大约75%。
Being a wireless radio communication technology suitable for short distance communication, UWB(Ultra-Wide Band)adapts ns pulse signal width with GHz signal frequency spectral and lower signal power. It becomes a hot point in the wireless radio communication area for its high distinguish ability, high intercepting ratio, more information content and detection ability on concealment. It is a key point to lower the error rate of transmission data in order to improve the reliability of communication. UWB system adapts the protocol which employs a (3,1,7) convolutional encoder and maximum likelihood Viterbi decoder in channel coding scheme when transmitting signal data.
Firstly, the basic concept and development of UWB technology at home and abroad is introduced in the thesis. Specifically for the channel characteristic of UWB, traditional error correct scheme convolutional coding and Viterbi decoding is adopted.
Secondly, consulting OFDM protocol, a (3,1,7) convolutional encoder and its Viterbi decoder is implemented, applying parallel mode, By using 4:2 compressors, the compare operations are concurrent with add operations in ACS unit. The circuit is described by Verilog Hardware Description Language, front simulated in ModelSim and some other tools. Soft decision information generated from Matlab simulation Platform resolves the difficulty of generating it. The thesis shows the simulation results of modules. Implementation of VLSI is used EDA tools.
Finally, the (3,1,7) Viterbi decoder circuit is verified in 132MHz system clock frequency, the result shows that it works well. Compared with serial mode, the ACS scheme saves about 75% timing.
首先总结了超宽带无线通信的基本概念和国内外发展动态。针对超宽带信道的特点,确定了信道编解码方案,即卷积码和基于Viterbi算法的译码方案,并且分析了Viterbi译码器的纠错性能。
其次,参照基于OFDM调制的物理层协议标准,设计并实现了(3,1,7)卷积码编码电路和Viterbi译码器。在关键路径的优化上,使用并行方式和新型的4:2压缩阵列设计了高速并行ACS电路。电路使用Verilog HDL语言进行描述,Modelsim软件等进行功能仿真。编码器采用Math Works公司的Matlab软件平台进行建模,并产生测试所需要的软判决信息。最后使用EDA工具对设计进行逻辑级优化和VLSI实现。
最后,验证结果表明,在系统时钟132MHz情况下,电路功能正确,满足了规范中的时序要求。其中,关键路径中的ACS模块的最高工作频率比传统的串行结构ACS提高了大约75%。
Being a wireless radio communication technology suitable for short distance communication, UWB(Ultra-Wide Band)adapts ns pulse signal width with GHz signal frequency spectral and lower signal power. It becomes a hot point in the wireless radio communication area for its high distinguish ability, high intercepting ratio, more information content and detection ability on concealment. It is a key point to lower the error rate of transmission data in order to improve the reliability of communication. UWB system adapts the protocol which employs a (3,1,7) convolutional encoder and maximum likelihood Viterbi decoder in channel coding scheme when transmitting signal data.
Firstly, the basic concept and development of UWB technology at home and abroad is introduced in the thesis. Specifically for the channel characteristic of UWB, traditional error correct scheme convolutional coding and Viterbi decoding is adopted.
Secondly, consulting OFDM protocol, a (3,1,7) convolutional encoder and its Viterbi decoder is implemented, applying parallel mode, By using 4:2 compressors, the compare operations are concurrent with add operations in ACS unit. The circuit is described by Verilog Hardware Description Language, front simulated in ModelSim and some other tools. Soft decision information generated from Matlab simulation Platform resolves the difficulty of generating it. The thesis shows the simulation results of modules. Implementation of VLSI is used EDA tools.
Finally, the (3,1,7) Viterbi decoder circuit is verified in 132MHz system clock frequency, the result shows that it works well. Compared with serial mode, the ACS scheme saves about 75% timing.
引文
[1]刘元安,宽带无线接入和无线局域网,北京邮电大学出版社,2000
[2]Ultra-Wideband Radio Technology[M],Kazimierz Siwiak,2005.
[3]王新梅,肖国镇.纠错码原理与方法[M].西安电子科技大学出版社,2001.
[4]美琳舒、科斯特洛,差错控制编码:基础和应用,(王育民、王新梅译),人民邮电出版社,1996.
[5]曹雪虹,张余橙.信息论与编码.北京:北京邮电大学出版社,2001
[6]Richard B.Wells.Applied Coding and information Theory for Engineers.机械工业出版社,2002
[7]S.Kubota,S.Kato,and T.Ishitani,"Novel Viterbi Decoder VLSI Implementation and Its Performance",IEEE Trans.Commun.,vol.41,no.8,pp.1170-1178,Aug.1993.
[8]P.J.Black and T.H.Meng,"A 140-Mb/s,32-State,Radix-4 Viterbi Decoder",IEEE J.Solid-State Circuits,vol.27,no.12,pp.1877-1885,Dec.1992.
[9]A.J.Viterbi,"Convolutional Codes and Their Performance in Communication Systems",IEEE Trans.Commun.,vol.COM-19,pp.751-772,Oct.1971.
[10]H.A.Bustamante,I.Kang,C.Nguyen,and R.E.Peile,"Stanford Telecom VLSI of A Convolutional Decoder",in Proc.,IEEE MILCOM,vol.1,pp.171-178,Oct.1989.
[11]R.Kerr,H.Dehesh,A.B.David,and D.Werner,"A 25 MHz Viterbi FEC Codec",in Proc,IEEE CICC,pp.16.6.1-16.6.5,May 1990.
[12]S.Kubota,K.Ohtani,and S.Kato,"High-speed and High-coding-gain Viterbi Decoder with Low Power Consumption Employing SST(scarce state transition)Scheme",Electron.Lett.,vol.22,Apr.1986.
[13]G.Fettweis and H.Meyr,"High-Speed Parallel Viterbi Decoding Algorithm and VLSI-Architecture",IEEE Commun.Mag.,vol.29,no.5,pp.46-55,May 1991.
[14]A.P.Hekstra,"An Alternative to Metric Rescaling in Viterbi Decoders",IEEE Trans.Commun.,vol.37,no.11,pp.1220-1222,Nov.1989.
[15]C.Berrou,A.Glavieux,P.Thitimajshima,Near Shannon Limit Error-Correcting Coding and Decoding:Turbo Codes,in Proceeding sof the International Conferenceon Communications,M y 1993.pp.1064-1070.
[16]Zhu,Y.,Benaissa,M..A novel ACS scheme for area-efficient Viterbi decoders,Proceedings of the 2003 International Symposium on Circuits and Systems, 2003,Volume 2:264-267.
[17] 王诚,吴继华,范丽珍, Altera FPGA/CPLD 设计,人民邮电出版社,2005。
[18] Mohiedin Wainakh, Isam Abboud, Mazen Morhej. Fast decoding Viterbi algorithm.Proceedings of 2004 International Conference on Information and CommunicationTechnologies: From Theory to Applications Publication Date, 2004 , page(s): 289 -290
[19] Irfan, M. , Shah, S.M. , Khan, A.K. .Design and Implementation of ViterbiEncoding and Decoding Algorithm on FPGA . 2005. ICM 2005. The 17th International Conference on Microelectronics, 2005 , page(s): 234 - 239
[20] Reeve, J.S. , Amarasinghe, K. .A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes.IEEE International Conference on Communications, 2004, Volume5 : 2596- 599
[21] Pandita, B. Roy, S.K., Design and implementation of a Viterbi decoder using FPGAs , VLSI Design, 1999. Proceedings. Twelfth International Conference On Publication Date:7-10 Jan. 1999 On page(s): 611-614
[22] Sudhakar, R., Mukhtar, A., Zhenzhong Gu .Low-complexity error selective Viterbi decoder. Electronics Letters ,2000,36(2): 147-148.
[23] Chen WHetal, A fast computational algorithm for the discrete cosine transform, IEEE Transactions on Communications, 1977.
[24] Byonghyo Shim,Jung Chul Suh,Pipelined VLSI Architecture of The ViterbiDecoder for IMT-2000,Globcom'99(PartA ),pp.158-162.
[25] E.Feig, S.Winograd, On the Multiplicative Complexity of Discrete Cosine Transforms, IEEE, 1992.
[26] Xun Liu, Marios C.Papaefthymiou,Design of a 20-Mb/s 256-State Viterbi De coder ,IEEE Transzctionson Very Large Scale Integration System,Vol. 11,No 6 December2003,pp.965-975..
[27] Chang-Wen Wang,Yun-Nan Chang "Design of Viterbi decoders with in-place state metric update and hybrid trace backprocessing Signal Processing Systems",2001 IEEE Work shop on,26-28Sept.2001
[28] David Akopian, amo Takala,Jukka Saarinen,Jaakko Astola. "Multistage Interconnection Net works for Parallel Viterbi Decoders In Communications",IEEE Transactionson,Volume:51 ,Issue:9,Sept.2003
[29] Engling Yeo,Augsburger S.A,David WR,NikolicB.A "500-Mb/s soft-output Viterbi decoder" Solid-State Circuits,IEEE Journal of,Volume:38,Issue:7,July2 003
[30] Sriram Swanrinathanect A Dynamic Reconfigurable A daptive Viterbi Decoder A FPGA02 2002.2.24-26
[31] Virtex-II Pro X Complete Data Sheet,www.altera.com
[32] Traber, M. .A low power survivor memory unit for sequential Viterbi-Decoders.IEEE International Symposium on Circuits and Systems ,2001, Volume 4:214-217.
[33] El-Dib, D.A. , Elmasry, M.I. . Modified register-exchange Viterbi decoder for low-power wireless communications.IEEE Transactions on Circuits and Systems I:Regular Papers, 2004,51(2):371-378
[34] LI Qiao, YOU Yuxin, WANG Jinxiang and YE Yizheng,"VLSI IMPLEMENTATION OF A HIGH-SPEED AND LOW-POWER PUNCTURED VITERBID ECODER",P roceedings of IEEE TENCON 02 ,pp.l2 05-8,2002
[35] Y.Zhu and Benaissa, a Novel ACS Scheme for Area-Efficient Viterbi Dcoders,IEEE, 2003. pp 264-267.
[36] GD.Fomey Jr . The Viterbi Algorithm , Proc.IEEE, Vol.61, March 1973, pp.268-278
[2]Ultra-Wideband Radio Technology[M],Kazimierz Siwiak,2005.
[3]王新梅,肖国镇.纠错码原理与方法[M].西安电子科技大学出版社,2001.
[4]美琳舒、科斯特洛,差错控制编码:基础和应用,(王育民、王新梅译),人民邮电出版社,1996.
[5]曹雪虹,张余橙.信息论与编码.北京:北京邮电大学出版社,2001
[6]Richard B.Wells.Applied Coding and information Theory for Engineers.机械工业出版社,2002
[7]S.Kubota,S.Kato,and T.Ishitani,"Novel Viterbi Decoder VLSI Implementation and Its Performance",IEEE Trans.Commun.,vol.41,no.8,pp.1170-1178,Aug.1993.
[8]P.J.Black and T.H.Meng,"A 140-Mb/s,32-State,Radix-4 Viterbi Decoder",IEEE J.Solid-State Circuits,vol.27,no.12,pp.1877-1885,Dec.1992.
[9]A.J.Viterbi,"Convolutional Codes and Their Performance in Communication Systems",IEEE Trans.Commun.,vol.COM-19,pp.751-772,Oct.1971.
[10]H.A.Bustamante,I.Kang,C.Nguyen,and R.E.Peile,"Stanford Telecom VLSI of A Convolutional Decoder",in Proc.,IEEE MILCOM,vol.1,pp.171-178,Oct.1989.
[11]R.Kerr,H.Dehesh,A.B.David,and D.Werner,"A 25 MHz Viterbi FEC Codec",in Proc,IEEE CICC,pp.16.6.1-16.6.5,May 1990.
[12]S.Kubota,K.Ohtani,and S.Kato,"High-speed and High-coding-gain Viterbi Decoder with Low Power Consumption Employing SST(scarce state transition)Scheme",Electron.Lett.,vol.22,Apr.1986.
[13]G.Fettweis and H.Meyr,"High-Speed Parallel Viterbi Decoding Algorithm and VLSI-Architecture",IEEE Commun.Mag.,vol.29,no.5,pp.46-55,May 1991.
[14]A.P.Hekstra,"An Alternative to Metric Rescaling in Viterbi Decoders",IEEE Trans.Commun.,vol.37,no.11,pp.1220-1222,Nov.1989.
[15]C.Berrou,A.Glavieux,P.Thitimajshima,Near Shannon Limit Error-Correcting Coding and Decoding:Turbo Codes,in Proceeding sof the International Conferenceon Communications,M y 1993.pp.1064-1070.
[16]Zhu,Y.,Benaissa,M..A novel ACS scheme for area-efficient Viterbi decoders,Proceedings of the 2003 International Symposium on Circuits and Systems, 2003,Volume 2:264-267.
[17] 王诚,吴继华,范丽珍, Altera FPGA/CPLD 设计,人民邮电出版社,2005。
[18] Mohiedin Wainakh, Isam Abboud, Mazen Morhej. Fast decoding Viterbi algorithm.Proceedings of 2004 International Conference on Information and CommunicationTechnologies: From Theory to Applications Publication Date, 2004 , page(s): 289 -290
[19] Irfan, M. , Shah, S.M. , Khan, A.K. .Design and Implementation of ViterbiEncoding and Decoding Algorithm on FPGA . 2005. ICM 2005. The 17th International Conference on Microelectronics, 2005 , page(s): 234 - 239
[20] Reeve, J.S. , Amarasinghe, K. .A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes.IEEE International Conference on Communications, 2004, Volume5 : 2596- 599
[21] Pandita, B. Roy, S.K., Design and implementation of a Viterbi decoder using FPGAs , VLSI Design, 1999. Proceedings. Twelfth International Conference On Publication Date:7-10 Jan. 1999 On page(s): 611-614
[22] Sudhakar, R., Mukhtar, A., Zhenzhong Gu .Low-complexity error selective Viterbi decoder. Electronics Letters ,2000,36(2): 147-148.
[23] Chen WHetal, A fast computational algorithm for the discrete cosine transform, IEEE Transactions on Communications, 1977.
[24] Byonghyo Shim,Jung Chul Suh,Pipelined VLSI Architecture of The ViterbiDecoder for IMT-2000,Globcom'99(PartA ),pp.158-162.
[25] E.Feig, S.Winograd, On the Multiplicative Complexity of Discrete Cosine Transforms, IEEE, 1992.
[26] Xun Liu, Marios C.Papaefthymiou,Design of a 20-Mb/s 256-State Viterbi De coder ,IEEE Transzctionson Very Large Scale Integration System,Vol. 11,No 6 December2003,pp.965-975..
[27] Chang-Wen Wang,Yun-Nan Chang "Design of Viterbi decoders with in-place state metric update and hybrid trace backprocessing Signal Processing Systems",2001 IEEE Work shop on,26-28Sept.2001
[28] David Akopian, amo Takala,Jukka Saarinen,Jaakko Astola. "Multistage Interconnection Net works for Parallel Viterbi Decoders In Communications",IEEE Transactionson,Volume:51 ,Issue:9,Sept.2003
[29] Engling Yeo,Augsburger S.A,David WR,NikolicB.A "500-Mb/s soft-output Viterbi decoder" Solid-State Circuits,IEEE Journal of,Volume:38,Issue:7,July2 003
[30] Sriram Swanrinathanect A Dynamic Reconfigurable A daptive Viterbi Decoder A FPGA02 2002.2.24-26
[31] Virtex-II Pro X Complete Data Sheet,www.altera.com
[32] Traber, M. .A low power survivor memory unit for sequential Viterbi-Decoders.IEEE International Symposium on Circuits and Systems ,2001, Volume 4:214-217.
[33] El-Dib, D.A. , Elmasry, M.I. . Modified register-exchange Viterbi decoder for low-power wireless communications.IEEE Transactions on Circuits and Systems I:Regular Papers, 2004,51(2):371-378
[34] LI Qiao, YOU Yuxin, WANG Jinxiang and YE Yizheng,"VLSI IMPLEMENTATION OF A HIGH-SPEED AND LOW-POWER PUNCTURED VITERBID ECODER",P roceedings of IEEE TENCON 02 ,pp.l2 05-8,2002
[35] Y.Zhu and Benaissa, a Novel ACS Scheme for Area-Efficient Viterbi Dcoders,IEEE, 2003. pp 264-267.
[36] GD.Fomey Jr . The Viterbi Algorithm , Proc.IEEE, Vol.61, March 1973, pp.268-278