基于FPGA的数字收发机信号处理研究与实现
摘要
在3G移动通信网络建设中,如何实现密集城区的无线网络覆盖是目前基站的发展方向。目前网络覆盖理念的核心思想就把传统宏基站的基带处理和射频部分分离,分成基带处理单元和射频拉远单元两个设备,这样既节省空间、降低设置成本,又提高了组网效率。本文研究的数字收发机用于WCDMA基站系统的射频拉远单元中,实现移动通信网中射频信号的传输工作。
数字收发机主要由射频处理部分、模数/数模转换部分、数字上下变频处理部分、接口转换以及数字光模块组成。本文研究的重点是数字上下变频处理部分。设计采用软件无线电的架构和FPGA技术,所设计的数字上下变频部分可以在不修改硬件电路的基础上只需修改软件部分的参数则可实现多种频率的变频处理,极大地降低了开发成本,且缩短了开发周期。
根据系统设计的设计要求,以及现有芯片使用情况比较,本文选用Altera公司的FPGA芯片,应用公司提供的Dspbuilder作为系统级的开发工具,应用QuartusⅡ作为综合、布局布线工具实现数字上下变频处理部分设计。
本文的主要研究工作包括以下几个部分:
(1)对数字收发机的整体结构进行分析研究,确定数字收发机的实现结构和各个部分的功能;
(2)通过对数字上下变频的相关理论的研究,分析出数字上下变频的结构、实现方法及性能;
(3)通过对数控振荡器、CIC滤波器、FIR滤波器进行理论研究、内部实现结构以及性能分析,得出具体的参数和仿真实现结构;
(4)使用FPGA中的IP核技术来实现数字上下变频,利用Matlab中Dspbuilder提供的IP核分别进行NCO、CIC、FIR的仿真工作;并得出数字上下变频的总体仿真实现结果;
(5)对高速收发通道进行了研究和设计,根据系统的要求给出了数据帧结构,并采用Altera的第三代FPGA产品StratixⅡGX系列芯片实现了数字收发机的信号的串并/并串的接口转换。为后续继续研究工作奠定基础。
Under the 3G mobile communications network constructions, the developing direction of base stations is how to achieve coverage of the City-intensive wireless network. Currently, the core of network coverage is to set the traditional macro base station apart into two equipments which are Baseband Unit and Radio Remote Unit. The digital transceiver discussed in this thesis is used to Radio Remote Unit in the WCDMA radio base station system, and to realize the transmission of radio signals in mobile communications network.
Digital transceiver is composed of RF treatment,AD/DA transformation, digital up or down converter, interface transformation and Digital optical modules. The focus is to deal with the digital up or down converter. Based on the structure of software radio and FPGA technology, digital up or down converter only be needed to modify parameters in software on the invariable hardware circuits, which could reduce development costs and shorten the research cycle greatly.
According to system design requirements and use comparison of existing chips,this paper selects Altera's FPGA and uses dspbuilder as the system level development tool, Quartus II as the synthesis,place and route tool to design the digital up or down converter.
The main tasks of this paper include the followings:
(1) Based on the analyzing and studying with the overall structure of digital transceiver, the structure of transceiver and functions are determined.
(2) By studying the theory of digital up or down converter, the structure, implementation and performance of digital up or down converter are analyzed.
(3) According to studying with the theory,inner structure and performance about NCO, CIC and FIR filter, specific parameters and simulation structures are proposed.
(4) The IP core in FPGAs is used to the design of digital up or down converter. And using the IP core proposed by dspbuilder in Matlab to finish simulation about NCO, CIC and FIR separately. The whole realizing result of digital up or down converter are achieved in this paper.
(5) Afer researching on the high-speed transmitter and receiver path, the data frame structure is provided based on the system requirements. Stratix II GX which is the Altera's third generation of FPGAs is used to realize serializer, deserializer interface transformation. This is established the foundation for the following-up research work.
数字收发机主要由射频处理部分、模数/数模转换部分、数字上下变频处理部分、接口转换以及数字光模块组成。本文研究的重点是数字上下变频处理部分。设计采用软件无线电的架构和FPGA技术,所设计的数字上下变频部分可以在不修改硬件电路的基础上只需修改软件部分的参数则可实现多种频率的变频处理,极大地降低了开发成本,且缩短了开发周期。
根据系统设计的设计要求,以及现有芯片使用情况比较,本文选用Altera公司的FPGA芯片,应用公司提供的Dspbuilder作为系统级的开发工具,应用QuartusⅡ作为综合、布局布线工具实现数字上下变频处理部分设计。
本文的主要研究工作包括以下几个部分:
(1)对数字收发机的整体结构进行分析研究,确定数字收发机的实现结构和各个部分的功能;
(2)通过对数字上下变频的相关理论的研究,分析出数字上下变频的结构、实现方法及性能;
(3)通过对数控振荡器、CIC滤波器、FIR滤波器进行理论研究、内部实现结构以及性能分析,得出具体的参数和仿真实现结构;
(4)使用FPGA中的IP核技术来实现数字上下变频,利用Matlab中Dspbuilder提供的IP核分别进行NCO、CIC、FIR的仿真工作;并得出数字上下变频的总体仿真实现结果;
(5)对高速收发通道进行了研究和设计,根据系统的要求给出了数据帧结构,并采用Altera的第三代FPGA产品StratixⅡGX系列芯片实现了数字收发机的信号的串并/并串的接口转换。为后续继续研究工作奠定基础。
Under the 3G mobile communications network constructions, the developing direction of base stations is how to achieve coverage of the City-intensive wireless network. Currently, the core of network coverage is to set the traditional macro base station apart into two equipments which are Baseband Unit and Radio Remote Unit. The digital transceiver discussed in this thesis is used to Radio Remote Unit in the WCDMA radio base station system, and to realize the transmission of radio signals in mobile communications network.
Digital transceiver is composed of RF treatment,AD/DA transformation, digital up or down converter, interface transformation and Digital optical modules. The focus is to deal with the digital up or down converter. Based on the structure of software radio and FPGA technology, digital up or down converter only be needed to modify parameters in software on the invariable hardware circuits, which could reduce development costs and shorten the research cycle greatly.
According to system design requirements and use comparison of existing chips,this paper selects Altera's FPGA and uses dspbuilder as the system level development tool, Quartus II as the synthesis,place and route tool to design the digital up or down converter.
The main tasks of this paper include the followings:
(1) Based on the analyzing and studying with the overall structure of digital transceiver, the structure of transceiver and functions are determined.
(2) By studying the theory of digital up or down converter, the structure, implementation and performance of digital up or down converter are analyzed.
(3) According to studying with the theory,inner structure and performance about NCO, CIC and FIR filter, specific parameters and simulation structures are proposed.
(4) The IP core in FPGAs is used to the design of digital up or down converter. And using the IP core proposed by dspbuilder in Matlab to finish simulation about NCO, CIC and FIR separately. The whole realizing result of digital up or down converter are achieved in this paper.
(5) Afer researching on the high-speed transmitter and receiver path, the data frame structure is provided based on the system requirements. Stratix II GX which is the Altera's third generation of FPGAs is used to realize serializer, deserializer interface transformation. This is established the foundation for the following-up research work.
引文
[1]王彦,倪琰,蒋伟,注晓维.3G数字基站射频拉远CPRI规范的实现.移动通信,2007.2-3:105-109
[2]杨小牛,楼才义,徐建良.软件无线电原理与应用.第一版.北京:电子工业出版社,2001
[3]Ming Jian,Weng Ho Yung,Bai Songrong.An efficient IF architecture for dual-mode GSM/W-CDMA receiver of a software radio,Mobile Multimedia Communications,1999.(MoMuC'99)1999 IEEE International Workshop on,15-17 Nov.1999
[4]Cummings M,Haruyama.FPGA in the software radio.IEEE Communications Magazine,1999,37(2):12-17
[5]中华人民共和国信息产业部.WCDMA数字蜂窝移动通信网——分布式基站的射频远端设备技术要求.2006
[6]张公礼.全数字接收机理论与技术.科学出版社.2005.1.
[7]ADI Corporation.AD6654 Data Sheet.2007
[8]ADI Corporation.AD9786 Data Sheet.2007
[9]杨小牛,邹少丞,楼才义.软件无线电技术与实现.北京:电子工业出版社,2004
[10]刘旭.软件无线电中数字上下变频器研究与实现:[硕士学位论文].成都:电子科技大学,2003
[11]樊昌信,张甫,徐炳祥,吴成柯.通信原理(第5版).北京:国防工业出版社,2001年
[12]谢文惠.基于FPGA的数字下变频技术的研究:[硕士学位论文].成都:成都理工大学,2007
[13]郑立岗.数字接收机若干技术研究及系统实现.成都:电子科技大学,2004
[14]程佩青.数字信号处理教程(第2版).北京:清华大学出版社.2004:334-387
[15]王静,杨梅,刘涛.半带抽取有限冲激响应滤波器的应用设计及仿真.大连海事大学学报,2004,30(2)
[16]张维良,郭兴波,潘长勇,杨知行.平方根升余弦滚降FIR数字滤波器的设计[J].电讯技术,2002,(6):51-55.
[17]张元,傅丰林,陈健.一种高效数字上变频器及其FPGA实现.空间电子技术.2006:47-51
[18]魏锋.数字上变频技术.长春理工大学学报.2006,29(1):63-66
[19]李鸿翔.可编程数字下变频器的关键技术[J].遥控遥测,2003,24(2):19-22
[20]Altera Corporation.DSPbuilder Userguide.2006
[21]崔文,叶信锋.基于查找表和CORDIC算法的数控振荡器的设计.电子科技.2006(7)
[22]郭书军,臧淼,张延华.数控振荡器应用及其在FPGA中的实现.微计算机信息,2006
[23]Altera Corporation.NCO Compiler User Guide.www.altera.com.2006
[24]曹李秋.软件无线电数字下变频FPGA实现的研究:[硕士学位论文].武汉:武汉理工大学,2006
[25]韦逸嘉.数字化中频接收机及其算法研究:[硕士学位论文].成都:电子科技大学,2005
[26]Alan Y.Kwentus,Zhongnong Jiang,and Alan N.Wilson,Jr.Application of filter sharpening to cascaded integrator-comb decimation filters.IEEE Transactions on Signal Processing,45(2):457-467,1997
[27]Altera Corporation.Understanding CIC Compensation Filters.2007
[28]Stephen G,Stewart R W.High-speed sharpening of decimating CIC filter.Elcctronics Letters.14th,Oct,2004,40(21)
[29]Altera Corporation.CIC Compiler User Guide.www.altera.com.2006
[30]李彬.FIR数字滤波器的FPGA实现技术研究:[硕士学位论文].成都:西南交通大学,2007
[31]赵文兵,杨建宁.FIR滤波器的FPGA实现及其仿真研究.微计算机信息.2005,21(7)
[32]Altera Corporation.FIR Compiler User Guide.www.altera.com.2007
[33]Stanley A W.Aplications of Distributed Arithmetic to Digital Signal Processing:A Tutorial Review[J].IEEE ASSP Magazine,1989,6(7):4-19
[34]He.S,Torkelson,M.FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers.In:Custom Integrated Circuits Conference,1994,Proceedings of the IEEE 1994 1-4 May 1994:81-84
[35]Altera Corporation.FIR Filters.www.altera.com.2007
[36]Davied B Chester.Digital IF Filter Technology for 3G Systems:An Introduction.IEEE Communications Magazine,February,1999
[37]薛年喜.MATLAB在数字信号处理中的应用[M].北京:清华大学出版社,2003:1-50
[38]文安平.平方根升余弦滚降数字滤波器的设计与实现.信息技术,2005,(9):58-60.
[39]E.B.Hogenauer.An economical class of digital filters for decimation and interpolation.IEEE Transactions on Acoustics,Speech and Signal Processing,ASSP-29(2):155-162,1981.
[40]Altera Corporation.Stratix Ⅱ GX Device Handbook.2007
[41]郭亚炜,张占鹏,章奕民,邱祖江,杨莲兴.一种1.25Gbps CMOS以太网串并/并串转换电路.微电子学.2003,33(1):53-55
[42]G.Ascheid,M.Oerder,J.Stahl,et all."An All Digital Receiver Architecture for Bandwidth Efficient Transmission At High Data Rates," IEEE Trans.on Comm,vol.37,Aug 1989.
[2]杨小牛,楼才义,徐建良.软件无线电原理与应用.第一版.北京:电子工业出版社,2001
[3]Ming Jian,Weng Ho Yung,Bai Songrong.An efficient IF architecture for dual-mode GSM/W-CDMA receiver of a software radio,Mobile Multimedia Communications,1999.(MoMuC'99)1999 IEEE International Workshop on,15-17 Nov.1999
[4]Cummings M,Haruyama.FPGA in the software radio.IEEE Communications Magazine,1999,37(2):12-17
[5]中华人民共和国信息产业部.WCDMA数字蜂窝移动通信网——分布式基站的射频远端设备技术要求.2006
[6]张公礼.全数字接收机理论与技术.科学出版社.2005.1.
[7]ADI Corporation.AD6654 Data Sheet.2007
[8]ADI Corporation.AD9786 Data Sheet.2007
[9]杨小牛,邹少丞,楼才义.软件无线电技术与实现.北京:电子工业出版社,2004
[10]刘旭.软件无线电中数字上下变频器研究与实现:[硕士学位论文].成都:电子科技大学,2003
[11]樊昌信,张甫,徐炳祥,吴成柯.通信原理(第5版).北京:国防工业出版社,2001年
[12]谢文惠.基于FPGA的数字下变频技术的研究:[硕士学位论文].成都:成都理工大学,2007
[13]郑立岗.数字接收机若干技术研究及系统实现.成都:电子科技大学,2004
[14]程佩青.数字信号处理教程(第2版).北京:清华大学出版社.2004:334-387
[15]王静,杨梅,刘涛.半带抽取有限冲激响应滤波器的应用设计及仿真.大连海事大学学报,2004,30(2)
[16]张维良,郭兴波,潘长勇,杨知行.平方根升余弦滚降FIR数字滤波器的设计[J].电讯技术,2002,(6):51-55.
[17]张元,傅丰林,陈健.一种高效数字上变频器及其FPGA实现.空间电子技术.2006:47-51
[18]魏锋.数字上变频技术.长春理工大学学报.2006,29(1):63-66
[19]李鸿翔.可编程数字下变频器的关键技术[J].遥控遥测,2003,24(2):19-22
[20]Altera Corporation.DSPbuilder Userguide.2006
[21]崔文,叶信锋.基于查找表和CORDIC算法的数控振荡器的设计.电子科技.2006(7)
[22]郭书军,臧淼,张延华.数控振荡器应用及其在FPGA中的实现.微计算机信息,2006
[23]Altera Corporation.NCO Compiler User Guide.www.altera.com.2006
[24]曹李秋.软件无线电数字下变频FPGA实现的研究:[硕士学位论文].武汉:武汉理工大学,2006
[25]韦逸嘉.数字化中频接收机及其算法研究:[硕士学位论文].成都:电子科技大学,2005
[26]Alan Y.Kwentus,Zhongnong Jiang,and Alan N.Wilson,Jr.Application of filter sharpening to cascaded integrator-comb decimation filters.IEEE Transactions on Signal Processing,45(2):457-467,1997
[27]Altera Corporation.Understanding CIC Compensation Filters.2007
[28]Stephen G,Stewart R W.High-speed sharpening of decimating CIC filter.Elcctronics Letters.14th,Oct,2004,40(21)
[29]Altera Corporation.CIC Compiler User Guide.www.altera.com.2006
[30]李彬.FIR数字滤波器的FPGA实现技术研究:[硕士学位论文].成都:西南交通大学,2007
[31]赵文兵,杨建宁.FIR滤波器的FPGA实现及其仿真研究.微计算机信息.2005,21(7)
[32]Altera Corporation.FIR Compiler User Guide.www.altera.com.2007
[33]Stanley A W.Aplications of Distributed Arithmetic to Digital Signal Processing:A Tutorial Review[J].IEEE ASSP Magazine,1989,6(7):4-19
[34]He.S,Torkelson,M.FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers.In:Custom Integrated Circuits Conference,1994,Proceedings of the IEEE 1994 1-4 May 1994:81-84
[35]Altera Corporation.FIR Filters.www.altera.com.2007
[36]Davied B Chester.Digital IF Filter Technology for 3G Systems:An Introduction.IEEE Communications Magazine,February,1999
[37]薛年喜.MATLAB在数字信号处理中的应用[M].北京:清华大学出版社,2003:1-50
[38]文安平.平方根升余弦滚降数字滤波器的设计与实现.信息技术,2005,(9):58-60.
[39]E.B.Hogenauer.An economical class of digital filters for decimation and interpolation.IEEE Transactions on Acoustics,Speech and Signal Processing,ASSP-29(2):155-162,1981.
[40]Altera Corporation.Stratix Ⅱ GX Device Handbook.2007
[41]郭亚炜,张占鹏,章奕民,邱祖江,杨莲兴.一种1.25Gbps CMOS以太网串并/并串转换电路.微电子学.2003,33(1):53-55
[42]G.Ascheid,M.Oerder,J.Stahl,et all."An All Digital Receiver Architecture for Bandwidth Efficient Transmission At High Data Rates," IEEE Trans.on Comm,vol.37,Aug 1989.