众核GPU体系结构相关技术研究
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摘要
大规模数据并行应用对可扩展性、计算能力和存储带宽的迫切需求促使高性能微处理器正在向众核体系结构演变。作为一种新型的众核体系结构,图形处理器(GPU)采用大量晶体管用于计算单元,采用相对简单的控制逻辑,具有非常高效的存储带宽层次。现代GPU体系结构所具有的片上计算单元密集、存储带宽高效、性价比高等鲜明的特点,形成了一个崭新的研究领域一基于GPU的通用计算(GPGPU),即利用GPU来实现更为广泛的数据并行计算。
受体系结构和可编程性的制约,早期的GPU未能在并行计算领域普及。随着高级编程模型(如AMD/ATI STREAM TM、NVIDIA CUDATM和OpenCL)的相继推出,GPU程序设计的复杂性在一定程度上得到降低。为了节约设计成本并实现未来体系结构的可扩展性,GPU体系结构通常采用分散式硬件设计。与CPU存储系统相比,GPU存储系统的设计目标是维持高吞吐量而非低延迟。虽然GPU体系结构可以同时维持大量的线程,以零开销的硬件线程切换来隐藏存储访问延迟,但是如果应用程序中存在大量的不规则数据访问,势必会造成很多线程因同时访存而出现暂停,浪费了宝贵的计算资源。GPU特殊的体系结构使得高级编程模型下的应用程序难以充分利用其强大的计算能力和高效的存储带宽,编写高性能的GPGPU程序需要考虑如何将应用程序有效映射至GPU硬件上加以执行。此外,GPU的并行编程模型与传统的串行编程模型存在差异,基于GPU体系结构的应用开发与优化方法也与传统方法有着很大不同。由于GPU体系结构底层硬件的复杂性,编译器并没有对应用程序进行充分的优化。为了指导应用程序高效映射到GPU体系结构上执行,本文研究了面向众核GPU体系结构的性能评估与优化方法,具体工作如下：
(1)当应用程序映射到GPU体系结构上执行时,很多因素都会降低程序的性能,一种量化的性能模型可以用于评估特定应用移植至GPU体系结构上的实际执行性能。由于现代GPU体系结构的复杂性,传统的并行计算模型无法用于评估GPGPU程序的性能。为了预测应用程序并行化后的执行性能,评估并行化过程中可能存在的性能瓶颈,本文针对GPU体系结构提出了一种量化的性能评估模型。该模型建立在抽象GPU体系结构和执行模型的基础上,充分考虑了影响GPGPU程序性能的各种因素(如全局存储器的接合访问、局部存储器的冲突访问、计算与存储访问重叠、条件分支转移、同步),在无需编写实际GPGPU程序的前提下,通过对应用程序的静态分析并结合GPU的性能参数设定具体的执行配置,即可估算出应用程序并行化后的执行时间。实验结果表明,该性能模型能够较为准确地评估应用程序在GPU体系结构上的执行时间。
(2)在GPU体系结构的存储系统中,全局存储器容量较大但访问延迟较高,快速存储器(如局部存储器)访问速度较快但容量有限。因此,改善数据在全局存储器中的布局,减少不规则存储访问,合理利用片上快速存储器,减少总体的存储访问开销对于提升GPGPU程序的性能至关重要。为了充分发挥GPU体系结构在存储带宽方面的优势,本文提出了基于多面体模型的存储优化方法。该方法建立源程序的多面体表示,分别对GPU的全局存储器和快速存储器进行优化与分配：通过检测存储访问模式,发掘可向量化的存储访问实例,利用数据空间变换对不规则存储访问模式进行转换,提高了GPU片外存储器的带宽利用率；通过检测程序中的数据重用,根据数据的访问属性和GPU存储器硬件的特性,实现了快速存储器的有效分配；采用坐标转换和增加偏移量的技术分别对IMAGE存储对象和局部存储器进行优化,提高了片上存储器的使用效率。实验结果表明,该存储优化方法可以使得程序的性能相对优化前提升1.2-8.4倍。
(3)循环和数组结构通常具有计算密集和数据并行的特征,因此这种结构通常是GPU计算核心的天然候选。然而在一些应用程序中,数据依赖和控制相关阻碍了它们在GPU体系结构上高效地运行。由于GPU体系结构同时强调计算密集与数据并行,因此将计算重构和数据重构加以组合更能够充分开发其性能潜力。为了使应用程序能够充分开发GPU体系结构的性能潜力,本文提出了面向GPU体系结构的程序重构方法：首先通过循环合并与拆分的计算重构增大了应用程序的可并行性,尽可能消除操作间的依赖关系,提高所生成GPU计算核心的计算密集性,有利于存储访问延迟的隐藏；其次,通过对线程内和线程问的数据访问进行重构,减少了GPU计算核心的存储访问次数；最后,通过条件执行、分支化简和间接索引等重构技术,减少了分支转移对于程序性能的负面影响。实验结果表明,该程序重构方法可以使得程序性能相对重构前提升1.18-2.56倍。
(4)数据并行应用中的非计算密集型算法存在存储墙问题,在基于GPU的并行化过程中显得更为突出。为了有效缓解存储受限型应用的存储墙问题,本文针对生物序列比对领域设计了一种基于GPU的Smith-Waterman并行算法：通过改变原有Smith-Waterman算法的计算流程和数据依赖关系,进一步增加了序列比对的并行性；通过实施面向GPU体系结构的优化方法,进一步提升了序列比对的性能和效率。实验结果表明,经过优化的Smith-Waterman算法与CPU上的串行算法相比提升了近115倍。
本文在众核GPU体系结构上的研究成果对今后在GPU上开发通用计算及面向其他众核体系结构的优化编译器方面具有借鉴意义。
High-performance microprocessor architectures have involved into many-core ones due to the demand for large-scale data-level parallel applications with respect to scalability, computational power and memory bandwidth. As novel many-core architecture, modern GPUs employ massive of transistors for ALU resources. Meanwhile, modern GPUs have relative simple control logic and very high-efficient memory bandwidth. These prominent characteristics make modern GPUs very feasible to be used in general-purpose data-parallel computing domains with high performance/cost ratio, which forms a new research area called general-purpose computing on GPUs (GPGPU).
Due to the constraint of architecture and programmability, earlier generations of GPUs do not be widely deployed in general-purpose computing domains. High-level programming models (e.g., ATM STREAMTM, NVIDIA CUDATM and OpenCL) reduce the learning curve of GPU programming. In order to save the design cost and maintain architectural scalability, modern GPUs always employ decentralized hardware framework. Compared with CPU memory system, GPU memory system is optimized for throughput rather than latency. GPUs are capable of supporting thousands of concurrently executing threads, with zero-cost hardware controlled context switching between threads to tolerance memory latency. However, many threads will access memory simultaneously if there are many irregular memory access patterns in the programs, which might waste computational resources by causing ALU stall. Hence, manual development of high-performance parallel codes for GPU architectures is still very challenging, because it is hard to fully exploit the architectural advantage of GPUs under high-level programming models. Achieving high performance need to consider how to effiently map these codes onto GPU hardware. Furthermore, given that there is significant difference between the sequential programming model for CPUs and the parallel programming model for GPUs, application development and optimization methods are diverse with respect to them. As a result of the complexity of the underlying hardware of GPU architectures, the compilers do not perform adequately optimizations. In order to fully exploit the computation capability of GPUs for general-purpose data-parallel computing, this paper investigates performance evaluation and optimization methods targeting GPU architectures. The contributions of this paper can be summarized as following:
(1) When porting application programs to GPU architectures, many factors will degrade performance. A quantitative performance model will help to determine the actual potential of a specific application program to port to GPU architectures. Due to the complex architecture of GPUs, traditional parallel performance models are not applicable. In order to evaluate the potential execution performance of an application programs and identify performance bottlenecks, this paper presents a quantitative GPGPU performance model. Based on the abstract GPU architecture, the present model embodies various features of the GPU architecture which affect the performance of a GPGPU kernel such as global memory access, local memory access, overlapping memory access with useful computation, conditional branch divergence and synchronization. By statically analyzing an application program with considering of the specific execution configuration, the present model can approximately estimate the execution time of an application program without the need of writing the actual GPGPU kernel. Analytical and experimental results show that the present model can estimate the execution time of application programs relative accurately.
(2) In GPU hierarchy memory system, global memory has larger size but with long access latency, fast memories (e.g., local memory) can be accessed with fast speed but with limited size. Hence, improving data layout in global memory to reduce irregular memory accesses and utilizing the fast memories effectively are crucial to reduce the overall overhead of memory accesses for a GPGPU kernel. In order to exerting the advantages of memory bandwidth of GPU architectures, this paper proposes memory optimization methods by means of polyhedral model. Polyhedral representation of a source program is built to optimize and allocate GPU memory system. By checking memory access patterns of the source program, access instances those can be grouped together are discovered by means of graph coloring. Subsequently, data space transformation is utilized to alter irregular memory access patterns for the sake of improving the off-chip memory bandwidth. Data reuse information is detected to allocate data into distinct fast memory regions according to both the properties of data accesses and the characteristics of the GPU memory model. Finally, coordinate conversion and offset inserting techniques are proposed with the purpose of optimizing the IMAGE memory object and the local memory bank conflict, making best usage of the fast on-chip memory. Experimental results for a set of benchmarks show that the optimized programs could achieve a speedup of 1.2x-8.4x compared to the un-optimized versions.
(3) The loop and array constructs exhibit inherent computation intensiveness and data parallelism, which are naturally been parallelized in a GPU kernel. However, some application programs exhibit complex dependence relationships and control flows, hindering them efficiently executing on GPU architectures. Given that GPU architectures emphasize both computation intensiveness and data parallelism, combination computation restructuring with data restructuring can better improve the performance of GPGPU kernels. In order to map data-parallel applications onto GPU architectures with high performance, this paper proposes program restructuring methods targeting GPU architectures. By computation restructuring with respect to loop incorporation and splitting, it enhances the parallelism and the compute intensity of the application programs, improving the ALU resources utilization of GPUs for better memory latency hiding. By inter-thread and intra-thread data restructuring, it eliminates the irregular data access patterns, reducing the number of memory access which improves the available memory bandwidth of the application programs. By branch restructuring such as conditional execution, branch predigesting and indirect indexing, it decrease the negative impact of branch divergence. Experimental results show that the proposed restructuring methods could achieve a speedup of 1.18x～2.56x compared to the un-restructured versions.
(4) During the parallelizing process of non-compute-intensive applications in GPU architectures, memory wall is a prominent problem. By designing and implementing a novel parallel Smith-Waterman algorithm in biological sequence alignment, this paper proposes a common optimization strategy for memory-bound applications targeting GPU architectures. It enhances the parallelism by altering the computation flows and data dependencies of the original Smith-Waterman algorithm and performs several architecture-aware optimizations, greatly improving the performance and efficiency of biological sequence alignment algorithm. Experimental results show that the proposed algorithm can achieve almost 115 times speedup, relieving the memory wall problem in data-parallel applications efficiently.
The performance evaluation model and optimization methods presented in this paper are helpful to provide insight for developing high-performance GPGPU applications and optimized compilers as well as other many-core achitectures.
受体系结构和可编程性的制约,早期的GPU未能在并行计算领域普及。随着高级编程模型(如AMD/ATI STREAM TM、NVIDIA CUDATM和OpenCL)的相继推出,GPU程序设计的复杂性在一定程度上得到降低。为了节约设计成本并实现未来体系结构的可扩展性,GPU体系结构通常采用分散式硬件设计。与CPU存储系统相比,GPU存储系统的设计目标是维持高吞吐量而非低延迟。虽然GPU体系结构可以同时维持大量的线程,以零开销的硬件线程切换来隐藏存储访问延迟,但是如果应用程序中存在大量的不规则数据访问,势必会造成很多线程因同时访存而出现暂停,浪费了宝贵的计算资源。GPU特殊的体系结构使得高级编程模型下的应用程序难以充分利用其强大的计算能力和高效的存储带宽,编写高性能的GPGPU程序需要考虑如何将应用程序有效映射至GPU硬件上加以执行。此外,GPU的并行编程模型与传统的串行编程模型存在差异,基于GPU体系结构的应用开发与优化方法也与传统方法有着很大不同。由于GPU体系结构底层硬件的复杂性,编译器并没有对应用程序进行充分的优化。为了指导应用程序高效映射到GPU体系结构上执行,本文研究了面向众核GPU体系结构的性能评估与优化方法,具体工作如下：
(1)当应用程序映射到GPU体系结构上执行时,很多因素都会降低程序的性能,一种量化的性能模型可以用于评估特定应用移植至GPU体系结构上的实际执行性能。由于现代GPU体系结构的复杂性,传统的并行计算模型无法用于评估GPGPU程序的性能。为了预测应用程序并行化后的执行性能,评估并行化过程中可能存在的性能瓶颈,本文针对GPU体系结构提出了一种量化的性能评估模型。该模型建立在抽象GPU体系结构和执行模型的基础上,充分考虑了影响GPGPU程序性能的各种因素(如全局存储器的接合访问、局部存储器的冲突访问、计算与存储访问重叠、条件分支转移、同步),在无需编写实际GPGPU程序的前提下,通过对应用程序的静态分析并结合GPU的性能参数设定具体的执行配置,即可估算出应用程序并行化后的执行时间。实验结果表明,该性能模型能够较为准确地评估应用程序在GPU体系结构上的执行时间。
(2)在GPU体系结构的存储系统中,全局存储器容量较大但访问延迟较高,快速存储器(如局部存储器)访问速度较快但容量有限。因此,改善数据在全局存储器中的布局,减少不规则存储访问,合理利用片上快速存储器,减少总体的存储访问开销对于提升GPGPU程序的性能至关重要。为了充分发挥GPU体系结构在存储带宽方面的优势,本文提出了基于多面体模型的存储优化方法。该方法建立源程序的多面体表示,分别对GPU的全局存储器和快速存储器进行优化与分配：通过检测存储访问模式,发掘可向量化的存储访问实例,利用数据空间变换对不规则存储访问模式进行转换,提高了GPU片外存储器的带宽利用率；通过检测程序中的数据重用,根据数据的访问属性和GPU存储器硬件的特性,实现了快速存储器的有效分配；采用坐标转换和增加偏移量的技术分别对IMAGE存储对象和局部存储器进行优化,提高了片上存储器的使用效率。实验结果表明,该存储优化方法可以使得程序的性能相对优化前提升1.2-8.4倍。
(3)循环和数组结构通常具有计算密集和数据并行的特征,因此这种结构通常是GPU计算核心的天然候选。然而在一些应用程序中,数据依赖和控制相关阻碍了它们在GPU体系结构上高效地运行。由于GPU体系结构同时强调计算密集与数据并行,因此将计算重构和数据重构加以组合更能够充分开发其性能潜力。为了使应用程序能够充分开发GPU体系结构的性能潜力,本文提出了面向GPU体系结构的程序重构方法：首先通过循环合并与拆分的计算重构增大了应用程序的可并行性,尽可能消除操作间的依赖关系,提高所生成GPU计算核心的计算密集性,有利于存储访问延迟的隐藏；其次,通过对线程内和线程问的数据访问进行重构,减少了GPU计算核心的存储访问次数；最后,通过条件执行、分支化简和间接索引等重构技术,减少了分支转移对于程序性能的负面影响。实验结果表明,该程序重构方法可以使得程序性能相对重构前提升1.18-2.56倍。
(4)数据并行应用中的非计算密集型算法存在存储墙问题,在基于GPU的并行化过程中显得更为突出。为了有效缓解存储受限型应用的存储墙问题,本文针对生物序列比对领域设计了一种基于GPU的Smith-Waterman并行算法：通过改变原有Smith-Waterman算法的计算流程和数据依赖关系,进一步增加了序列比对的并行性；通过实施面向GPU体系结构的优化方法,进一步提升了序列比对的性能和效率。实验结果表明,经过优化的Smith-Waterman算法与CPU上的串行算法相比提升了近115倍。
本文在众核GPU体系结构上的研究成果对今后在GPU上开发通用计算及面向其他众核体系结构的优化编译器方面具有借鉴意义。
High-performance microprocessor architectures have involved into many-core ones due to the demand for large-scale data-level parallel applications with respect to scalability, computational power and memory bandwidth. As novel many-core architecture, modern GPUs employ massive of transistors for ALU resources. Meanwhile, modern GPUs have relative simple control logic and very high-efficient memory bandwidth. These prominent characteristics make modern GPUs very feasible to be used in general-purpose data-parallel computing domains with high performance/cost ratio, which forms a new research area called general-purpose computing on GPUs (GPGPU).
Due to the constraint of architecture and programmability, earlier generations of GPUs do not be widely deployed in general-purpose computing domains. High-level programming models (e.g., ATM STREAMTM, NVIDIA CUDATM and OpenCL) reduce the learning curve of GPU programming. In order to save the design cost and maintain architectural scalability, modern GPUs always employ decentralized hardware framework. Compared with CPU memory system, GPU memory system is optimized for throughput rather than latency. GPUs are capable of supporting thousands of concurrently executing threads, with zero-cost hardware controlled context switching between threads to tolerance memory latency. However, many threads will access memory simultaneously if there are many irregular memory access patterns in the programs, which might waste computational resources by causing ALU stall. Hence, manual development of high-performance parallel codes for GPU architectures is still very challenging, because it is hard to fully exploit the architectural advantage of GPUs under high-level programming models. Achieving high performance need to consider how to effiently map these codes onto GPU hardware. Furthermore, given that there is significant difference between the sequential programming model for CPUs and the parallel programming model for GPUs, application development and optimization methods are diverse with respect to them. As a result of the complexity of the underlying hardware of GPU architectures, the compilers do not perform adequately optimizations. In order to fully exploit the computation capability of GPUs for general-purpose data-parallel computing, this paper investigates performance evaluation and optimization methods targeting GPU architectures. The contributions of this paper can be summarized as following:
(1) When porting application programs to GPU architectures, many factors will degrade performance. A quantitative performance model will help to determine the actual potential of a specific application program to port to GPU architectures. Due to the complex architecture of GPUs, traditional parallel performance models are not applicable. In order to evaluate the potential execution performance of an application programs and identify performance bottlenecks, this paper presents a quantitative GPGPU performance model. Based on the abstract GPU architecture, the present model embodies various features of the GPU architecture which affect the performance of a GPGPU kernel such as global memory access, local memory access, overlapping memory access with useful computation, conditional branch divergence and synchronization. By statically analyzing an application program with considering of the specific execution configuration, the present model can approximately estimate the execution time of an application program without the need of writing the actual GPGPU kernel. Analytical and experimental results show that the present model can estimate the execution time of application programs relative accurately.
(2) In GPU hierarchy memory system, global memory has larger size but with long access latency, fast memories (e.g., local memory) can be accessed with fast speed but with limited size. Hence, improving data layout in global memory to reduce irregular memory accesses and utilizing the fast memories effectively are crucial to reduce the overall overhead of memory accesses for a GPGPU kernel. In order to exerting the advantages of memory bandwidth of GPU architectures, this paper proposes memory optimization methods by means of polyhedral model. Polyhedral representation of a source program is built to optimize and allocate GPU memory system. By checking memory access patterns of the source program, access instances those can be grouped together are discovered by means of graph coloring. Subsequently, data space transformation is utilized to alter irregular memory access patterns for the sake of improving the off-chip memory bandwidth. Data reuse information is detected to allocate data into distinct fast memory regions according to both the properties of data accesses and the characteristics of the GPU memory model. Finally, coordinate conversion and offset inserting techniques are proposed with the purpose of optimizing the IMAGE memory object and the local memory bank conflict, making best usage of the fast on-chip memory. Experimental results for a set of benchmarks show that the optimized programs could achieve a speedup of 1.2x-8.4x compared to the un-optimized versions.
(3) The loop and array constructs exhibit inherent computation intensiveness and data parallelism, which are naturally been parallelized in a GPU kernel. However, some application programs exhibit complex dependence relationships and control flows, hindering them efficiently executing on GPU architectures. Given that GPU architectures emphasize both computation intensiveness and data parallelism, combination computation restructuring with data restructuring can better improve the performance of GPGPU kernels. In order to map data-parallel applications onto GPU architectures with high performance, this paper proposes program restructuring methods targeting GPU architectures. By computation restructuring with respect to loop incorporation and splitting, it enhances the parallelism and the compute intensity of the application programs, improving the ALU resources utilization of GPUs for better memory latency hiding. By inter-thread and intra-thread data restructuring, it eliminates the irregular data access patterns, reducing the number of memory access which improves the available memory bandwidth of the application programs. By branch restructuring such as conditional execution, branch predigesting and indirect indexing, it decrease the negative impact of branch divergence. Experimental results show that the proposed restructuring methods could achieve a speedup of 1.18x～2.56x compared to the un-restructured versions.
(4) During the parallelizing process of non-compute-intensive applications in GPU architectures, memory wall is a prominent problem. By designing and implementing a novel parallel Smith-Waterman algorithm in biological sequence alignment, this paper proposes a common optimization strategy for memory-bound applications targeting GPU architectures. It enhances the parallelism by altering the computation flows and data dependencies of the original Smith-Waterman algorithm and performs several architecture-aware optimizations, greatly improving the performance and efficiency of biological sequence alignment algorithm. Experimental results show that the proposed algorithm can achieve almost 115 times speedup, relieving the memory wall problem in data-parallel applications efficiently.
The performance evaluation model and optimization methods presented in this paper are helpful to provide insight for developing high-performance GPGPU applications and optimized compilers as well as other many-core achitectures.
引文
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