新型DSP访存系统研究与设计
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摘要
作为下一代无线通信主流系统实现技术,软件无线电是无线通信基站处理平台的理想解决方案,采用软件无线电技术实现LTE协议基站的关键问题在于数字信号处理系统的设计。存储系统是数字信号处理系统的重要组成部分,它的设计成败以及性能高低直接影响着数字信号处理系统设计的成败。FT-Matrix DSP是一款完成LTE协议物理层演算的高性能数字信号处理器,它具有独立的向量处理单元和标量处理单元,能够并发执行向量指令和标量指令,向量处理单元有16个PE处理向量指令。本文以FT-Matrix DSP体系结构作为研究背景,研究LTE协议基带处理核心操作和算法流程以及相关操作和算法,分析系统的数据需求;根据数据需求,研究并设计满足LTE协议基站端基带处理需求的访存系统体系结构;根据访存体系结构的特点,设计访存指令集、标量访存系统以及向量访存系统;最后采用模拟验证的方法验证设计功能并综合优化电路系统。
本文的主要内容集中在访存指令集设计、标量访存系统设计和向量访存系统设计三个方面。访存指令集的主要设计内容包括指令格式设计、指令功能设计以及寻址模式设计。标量访存系统的主要设计内容包括访存控制器的设计、存储体设计和DCache的设计。其中DCache采用了新型算法实现,提高了命中率并降低了缺失处理损失。向量访存系统的主要设计内容包括存储体结构设计和访存控制器的设计。
文章采用模拟验证方法在模块级和系统级进行了充分的功能验证,开发了有效的、完备的验证码,构建了验证模型,验证了设计的正确性。最后阐述了该部件的逻辑综合过程,结果表明该单元在65纳米工艺下的工作频率为500MHz左右,达到了所要求的性能指标。
As the mainstream technology of the next generation wireless communication system, SDR(software defined radio) is a promising solution of wireless communication basestation process platform. One of the key issues in using software radio technology to realize baseband calculation for LTE protocol is the design of digital signal processing system As a important part of digital signal processing, memory system affects the success of digital signal processing system significantly. FT-Matrix DSP is a high-performance digital signal processor that executes the process of physical layer of LTE protocol, which has an independent vector processing unit and scalar processing unit. It can processes vector instructions and scalar instructions in parallel. The vector processing unit supports 16 vector instructions. Based on the FT-Matrix DSP architecture, we research kernel operation andalgorithm procedures of LTE protocol baseband processing. After the analysis of data demand of LTE protocol basestation system, we design the memory access system. According to the feature of memory acesss system, the memory aceess instruction set, scalar access system and vectror access system. Finaly, simulation is adopted to verify the function of the design and optimization.
This paper focuses on the designs of memory access instruction set, scalar access system and vector access system. Memory access instructin contains the design of instruction format, instruction function and address access mode. Scalar access system includes the design of memory controller, memory bank and DCache, where a novel algorithm is implemented in DCahce to improve the hit rate and reduce the cost of miss. The vector access is comprised of the design of memory bank and memory controller.
By developing an efficient and self-contained testbench, we simulate the design on both module level and system level. The result shows the correctness of this design. At the end of this paper, we discuss the synthesis of the memory access system.The synthesis results show that the the unit’s clock frequency are 500MHz in 65nm CMOS technology, which is consist with our expection.
本文的主要内容集中在访存指令集设计、标量访存系统设计和向量访存系统设计三个方面。访存指令集的主要设计内容包括指令格式设计、指令功能设计以及寻址模式设计。标量访存系统的主要设计内容包括访存控制器的设计、存储体设计和DCache的设计。其中DCache采用了新型算法实现,提高了命中率并降低了缺失处理损失。向量访存系统的主要设计内容包括存储体结构设计和访存控制器的设计。
文章采用模拟验证方法在模块级和系统级进行了充分的功能验证,开发了有效的、完备的验证码,构建了验证模型,验证了设计的正确性。最后阐述了该部件的逻辑综合过程,结果表明该单元在65纳米工艺下的工作频率为500MHz左右,达到了所要求的性能指标。
As the mainstream technology of the next generation wireless communication system, SDR(software defined radio) is a promising solution of wireless communication basestation process platform. One of the key issues in using software radio technology to realize baseband calculation for LTE protocol is the design of digital signal processing system As a important part of digital signal processing, memory system affects the success of digital signal processing system significantly. FT-Matrix DSP is a high-performance digital signal processor that executes the process of physical layer of LTE protocol, which has an independent vector processing unit and scalar processing unit. It can processes vector instructions and scalar instructions in parallel. The vector processing unit supports 16 vector instructions. Based on the FT-Matrix DSP architecture, we research kernel operation andalgorithm procedures of LTE protocol baseband processing. After the analysis of data demand of LTE protocol basestation system, we design the memory access system. According to the feature of memory acesss system, the memory aceess instruction set, scalar access system and vectror access system. Finaly, simulation is adopted to verify the function of the design and optimization.
This paper focuses on the designs of memory access instruction set, scalar access system and vector access system. Memory access instructin contains the design of instruction format, instruction function and address access mode. Scalar access system includes the design of memory controller, memory bank and DCache, where a novel algorithm is implemented in DCahce to improve the hit rate and reduce the cost of miss. The vector access is comprised of the design of memory bank and memory controller.
By developing an efficient and self-contained testbench, we simulate the design on both module level and system level. The result shows the correctness of this design. At the end of this paper, we discuss the synthesis of the memory access system.The synthesis results show that the the unit’s clock frequency are 500MHz in 65nm CMOS technology, which is consist with our expection.
引文
[1] Wally H. W. Tuttlebee. Software defined radio: enabling technologies. WILEY.2002.
[2] C..van Berkel et al. Vector Processing as an Enabler for Software-DeFined Radio in Handsets From 3G+WLAN Onwards. In Proc. 2004 Software De_ned Radio Technical Conference, Nov. 2004.
[3]沈嘉,索士强,全海洋等编著,3GPP长期演进(LTE)技术原理与系统设计,北京:人民邮电出版社
[4] Bernard Sklar,数字通信,北京:电子工业出版社, 2008
[5]邱玲,住进康,孙宝根等,第三代移动通信技术,北京:人民邮电出版社, 2001
[6]沈嘉. 3GPP LTE核心技术及标准化进展.移动通信, 2006(4).
[7] 3GPP R1-072444, Ericsson. Summary of Downlink Performance Evaluation, 3GPP TSG RAN WG1 Meeting#41.
[8]曹淑敏.通信技术与标准.无线移动通信发展趋势, 2005.
[9]谢刚. FT_Matrix DSP向量MAC单元设计与实现,国防科技大学研究生院,硕士学位论文, 2011
[10]戴逸民,梁晓雯,基于DSP的现代电子技术系统设计,电子工业出版社,2007
[11] Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott Mahlke et al. SODA: A High-Performance DSP Architecture for Software-Defined Radio. IEEE Micro, vol. 27, no. 1, pp. 114-123.
[12]卞红雨,纪祥春等译,4TMS320C6000系列DSP的CPU与外设,清华大学出版社,2005
[13]陈书明,万江华,郭阳,高性能数字信号处理器研究进展,第九届计算机工程与工艺全国年会,2004.8
[14] Hanan Weingarten, Yossef Steinberg, Shlomo Shamai. The Capacity Region of the Gaussian Multiple-Input Multiple-Output Broadcast Channel, IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 52, NO. 9, SEPTEMBER 2006.
[15] John L. Henessy, David A. Patterson, Computer Architecture: A Quantitative Approach, Third Edition, 2004
[16] TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Literature Number: SPRU732J. July 2010.
[17]李勇,裘式纲,王凤学,宋焕章,计算机原理与设计,长沙:国防科技大学出版社, 1985
[18]石教英,计算机体系结构,浙江大学出版社,2008
[19]张晨曦,计算机体系结构,2009
[20] David A.Patterson, John L.Hennessy,Computer organizations and design the hardware/software interface,third edition
[21] SPRU610 TMS320C64x DSP Two_Level Internal Memory Reference Guide. Texas Instrument,2002
[22] Sadagopan Srinivasan, Vinodh Cuppu,Transparent Data-Memory Organizations for Digital Signal Processors,International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), pp. 44-48, 2001,11
[23] Brian R Gaeke, Parry Husbands, Xiaoye S Li, Memory-intensive benchmarks:IRAM vs. cache-based machines, iram.cs.Berkeley.edu/papers, 2002
[24] MS320C62x, TMS320C67x DSP Cache Performance on Vocoder Benchmarks, www.ti.com
[25]马鹏勇等,支持两条并行存储指令的Cache控制器设计,高技术通信增刊,2002.8
[26] J. L. Hennessy and D. A. Patterson, Computer Architecture a Quantitative Approach (Third Edition), Elservier Science Pte Ltd., 2002
[27] Bill S.H.Kwan, Bruce F.Cockburn, Implementation of DSP-RAM:An Architecture for Parallel Digital Signal Processing In Memory, Electrical and Computer Engineering Conference, Canadian, 2001
[28]周文华,罗晓沛,专用集成电路的设计验证方法及一种实际的通用微处理器设计的多级验证体系,计算机研究与发展,pp.764-768, 1999,6(6)
[29] David Dempster, Michael Stuart, VERIFICATION METHO-DOLOGY MANUAL Techniques for Verifying HDL Designs, pp.34, Team work International, 1998
[30]数字信号处理实践方法(第二版) Emmanuel C .Ifeachor Barrie W. Jervis电子工业出版社545-546页
[31]夏宇闻,复杂数字电路与系统的Verilog HDL设计技术,北京:北京航空航天大学, 1998
[32] Guide to HDL Coding Styles for Synthesis, Synopsys Corp.2003.3
[33] HIimianshu Bhatnagar,Advanced ASIC chip synthesis,Kluwer academic publishers,2002
[34] Advanced ASIC chip synthesis , Himianshu Bhatnagar , Kluwer academic publishers,2002
[2] C..van Berkel et al. Vector Processing as an Enabler for Software-DeFined Radio in Handsets From 3G+WLAN Onwards. In Proc. 2004 Software De_ned Radio Technical Conference, Nov. 2004.
[3]沈嘉,索士强,全海洋等编著,3GPP长期演进(LTE)技术原理与系统设计,北京:人民邮电出版社
[4] Bernard Sklar,数字通信,北京:电子工业出版社, 2008
[5]邱玲,住进康,孙宝根等,第三代移动通信技术,北京:人民邮电出版社, 2001
[6]沈嘉. 3GPP LTE核心技术及标准化进展.移动通信, 2006(4).
[7] 3GPP R1-072444, Ericsson. Summary of Downlink Performance Evaluation, 3GPP TSG RAN WG1 Meeting#41.
[8]曹淑敏.通信技术与标准.无线移动通信发展趋势, 2005.
[9]谢刚. FT_Matrix DSP向量MAC单元设计与实现,国防科技大学研究生院,硕士学位论文, 2011
[10]戴逸民,梁晓雯,基于DSP的现代电子技术系统设计,电子工业出版社,2007
[11] Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott Mahlke et al. SODA: A High-Performance DSP Architecture for Software-Defined Radio. IEEE Micro, vol. 27, no. 1, pp. 114-123.
[12]卞红雨,纪祥春等译,4TMS320C6000系列DSP的CPU与外设,清华大学出版社,2005
[13]陈书明,万江华,郭阳,高性能数字信号处理器研究进展,第九届计算机工程与工艺全国年会,2004.8
[14] Hanan Weingarten, Yossef Steinberg, Shlomo Shamai. The Capacity Region of the Gaussian Multiple-Input Multiple-Output Broadcast Channel, IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 52, NO. 9, SEPTEMBER 2006.
[15] John L. Henessy, David A. Patterson, Computer Architecture: A Quantitative Approach, Third Edition, 2004
[16] TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Literature Number: SPRU732J. July 2010.
[17]李勇,裘式纲,王凤学,宋焕章,计算机原理与设计,长沙:国防科技大学出版社, 1985
[18]石教英,计算机体系结构,浙江大学出版社,2008
[19]张晨曦,计算机体系结构,2009
[20] David A.Patterson, John L.Hennessy,Computer organizations and design the hardware/software interface,third edition
[21] SPRU610 TMS320C64x DSP Two_Level Internal Memory Reference Guide. Texas Instrument,2002
[22] Sadagopan Srinivasan, Vinodh Cuppu,Transparent Data-Memory Organizations for Digital Signal Processors,International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), pp. 44-48, 2001,11
[23] Brian R Gaeke, Parry Husbands, Xiaoye S Li, Memory-intensive benchmarks:IRAM vs. cache-based machines, iram.cs.Berkeley.edu/papers, 2002
[24] MS320C62x, TMS320C67x DSP Cache Performance on Vocoder Benchmarks, www.ti.com
[25]马鹏勇等,支持两条并行存储指令的Cache控制器设计,高技术通信增刊,2002.8
[26] J. L. Hennessy and D. A. Patterson, Computer Architecture a Quantitative Approach (Third Edition), Elservier Science Pte Ltd., 2002
[27] Bill S.H.Kwan, Bruce F.Cockburn, Implementation of DSP-RAM:An Architecture for Parallel Digital Signal Processing In Memory, Electrical and Computer Engineering Conference, Canadian, 2001
[28]周文华,罗晓沛,专用集成电路的设计验证方法及一种实际的通用微处理器设计的多级验证体系,计算机研究与发展,pp.764-768, 1999,6(6)
[29] David Dempster, Michael Stuart, VERIFICATION METHO-DOLOGY MANUAL Techniques for Verifying HDL Designs, pp.34, Team work International, 1998
[30]数字信号处理实践方法(第二版) Emmanuel C .Ifeachor Barrie W. Jervis电子工业出版社545-546页
[31]夏宇闻,复杂数字电路与系统的Verilog HDL设计技术,北京:北京航空航天大学, 1998
[32] Guide to HDL Coding Styles for Synthesis, Synopsys Corp.2003.3
[33] HIimianshu Bhatnagar,Advanced ASIC chip synthesis,Kluwer academic publishers,2002
[34] Advanced ASIC chip synthesis , Himianshu Bhatnagar , Kluwer academic publishers,2002