动态扩展相容性扫描树
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摘要
全扫描测试是最有效和流行的可测性设计技术之一。全扫描测试技术将时序电路的测试产生问题转化为组合电路的测试产生问题,降低了测试生成的复杂度,并提高了故障覆盖率。但是,测试应用时间、测试数据量和测试功耗都大大增加。全扫描测试技术的测试应用时间依赖于扫描链的长度。压缩扫描测试结构依靠引入扫描链并行模式减少了大量测试应用时间,考虑到外部扫描端口与内部扫描链之间的关联性制约,如何在输入端桥接外部扫描输入与内部多条并联扫描链是一个较为复杂的问题且不得不折中考虑其它因素。对此,基于扫描单元相容性构造的扫描测试结构应运而生,一种是测试向量在不同相容类的扫描单元之间以扩散方式传递,如扫描树技术；另一种是测试向量在同一相容类的扫描单元之间以数据拷贝的方式传递,如DCScan结构。它们都极大地降低了测试应用时间与测试功耗。本文基于扫描树结构和DCScan结构展开研究。
针对扫描树测试结构中树形扩散扫描方式存在的三个问题：冗余功耗较大,输出端口太多,测试响应压缩容易产生别名,本文提出了一种低硬件开销的动态扫描树结构。该结构通过扫描链阻塞和输出路径的动态重组,解决了上述问题,并兼容多扫描链压缩器。实验结果表明了该结构的性能,对于ISCAS’89标准电路,对比原扩展相容性扫描树结构,在测试响应的数据量最多平均减少97.19%时,测试功耗平均降低36.4%；在测试响应的数据量平均减少88.77%时,测试功耗平均降低69.6%。
针对基于扫描单元相容性构造的扫描测试结构中测试响应同步输出引发的问题,本文提出了分时激活扫描输出方法。在动态扩展相容性扫描树结构中,分时激活输出能在保持最少输出时降低大量的功耗；在DCScan结构中,分时激活输出方法极大地减少了输出端口数,并降低了扫描移位时的峰值功耗。
Full-scan test is one of the most effective and popular design for testability technologies. Full-scan test technology changes the sequential circuit testing problem into the combinational circuit test problems, reducing the complexity of test generation and meanwhile increasing the coverage of faults but with great increase of the application time, data volume and power consumption of the test. Test application time in Full-scan test technology depends on the length of the longest scan chain. Due to the introduction of parallel scan chain mode, compressed scan test structures reduces a large number of test application time, but how to bridge the gap between external scan ports and a large number of internal scan chains in parallel on the input side is a complicated issue which should be settled by taking other factors into account because of the strong constraints at the interface between external scan ports and internal scan chains. In this regard, the scan test architecture based on scan cell compatibility came into being, one is to diffuse test vectors between scan cells in different compatible sets, such as scan tree architecture; The other is to copy test vectors between scan cells in the same compatible set, such as DCScan architecture. This thesis makes a study on scan tree architecture and DCScan architecture.
In terms of three problems in tree-proliferation scanning for scan tree architecture-redundant power, excessive output ports and easy producing alias in response to compact, this thesis proposes a dynamic scan tree architecture which has low additional hardware overhead. The above problems are solved by scan chain disable and dynamic reconfiguration of scan path. Moreover, multiple scan chain compactors are compatible. The results show the performance of the architecture. As for the ISCAS'89 benchmark circuits, the average test response data volume is reduced by 97.19%at most compared with the original extended compatibilities scan tree architecture and is decreased by 88.77%when the test power on average is in 69.6%reduction.
In terms of problems caused by synchronously outputting test response in the scan test architecture based on scan cell compatibility, this thesis proposes time-division-activated scan-output method. In the extended compatibilities scan tree architecture, this method can reduce a large number of test power while maintaining a minimum output; In DCScan architecture, this method greatly reduces the number of output ports and reduces peak power when scan shifting.
针对扫描树测试结构中树形扩散扫描方式存在的三个问题：冗余功耗较大,输出端口太多,测试响应压缩容易产生别名,本文提出了一种低硬件开销的动态扫描树结构。该结构通过扫描链阻塞和输出路径的动态重组,解决了上述问题,并兼容多扫描链压缩器。实验结果表明了该结构的性能,对于ISCAS’89标准电路,对比原扩展相容性扫描树结构,在测试响应的数据量最多平均减少97.19%时,测试功耗平均降低36.4%；在测试响应的数据量平均减少88.77%时,测试功耗平均降低69.6%。
针对基于扫描单元相容性构造的扫描测试结构中测试响应同步输出引发的问题,本文提出了分时激活扫描输出方法。在动态扩展相容性扫描树结构中,分时激活输出能在保持最少输出时降低大量的功耗；在DCScan结构中,分时激活输出方法极大地减少了输出端口数,并降低了扫描移位时的峰值功耗。
Full-scan test is one of the most effective and popular design for testability technologies. Full-scan test technology changes the sequential circuit testing problem into the combinational circuit test problems, reducing the complexity of test generation and meanwhile increasing the coverage of faults but with great increase of the application time, data volume and power consumption of the test. Test application time in Full-scan test technology depends on the length of the longest scan chain. Due to the introduction of parallel scan chain mode, compressed scan test structures reduces a large number of test application time, but how to bridge the gap between external scan ports and a large number of internal scan chains in parallel on the input side is a complicated issue which should be settled by taking other factors into account because of the strong constraints at the interface between external scan ports and internal scan chains. In this regard, the scan test architecture based on scan cell compatibility came into being, one is to diffuse test vectors between scan cells in different compatible sets, such as scan tree architecture; The other is to copy test vectors between scan cells in the same compatible set, such as DCScan architecture. This thesis makes a study on scan tree architecture and DCScan architecture.
In terms of three problems in tree-proliferation scanning for scan tree architecture-redundant power, excessive output ports and easy producing alias in response to compact, this thesis proposes a dynamic scan tree architecture which has low additional hardware overhead. The above problems are solved by scan chain disable and dynamic reconfiguration of scan path. Moreover, multiple scan chain compactors are compatible. The results show the performance of the architecture. As for the ISCAS'89 benchmark circuits, the average test response data volume is reduced by 97.19%at most compared with the original extended compatibilities scan tree architecture and is decreased by 88.77%when the test power on average is in 69.6%reduction.
In terms of problems caused by synchronously outputting test response in the scan test architecture based on scan cell compatibility, this thesis proposes time-division-activated scan-output method. In the extended compatibilities scan tree architecture, this method can reduce a large number of test power while maintaining a minimum output; In DCScan architecture, this method greatly reduces the number of output ports and reduces peak power when scan shifting.
引文
[1]贾新章,郝跃.微电子技术概论.第1版.北京：国防工业出版社,1995,35-36
[2]Paul H. B, Mcanney W. H, Savir J. Built-in Test for VLSI Pseudorandom Techniques. Wiley-Interscience. NY:1987,151-153
[3]Bennetts R. Design of Testable Logic Circuits. Addison-Wesley. London: 1984,74-77
[4]Timoc C, Buehler M L, Griswold T, et al. Logical Models of Physical Failures. In: Proc of International Test Conference. Philadelphia,1983,546-553
[5]Bushnell M L and Agrawal V D. Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits. USA:Kluwer Academic Publishers, 2000,13-14
[6]Miron Abramovici,Melvin A.Breuer,Arthur D.Friedman.数字系统的测试与可测性设计.北京：机械工业出版社,2006,87
[7]Goldstein L H and Thigpen E L. SCOAP:Sandia Controllability/Observability Analysis Program. In:Proc of the 17th Design Automation Conference. Las Vegas,1980,190-196
[8]Agrawal V D and Mercer M R. Testability Measures-What Do They Tell Us. In: Proc of International Test Conference. Philadelphia,1982,391-396
[9]Seth S C and Agrawal V D. A New Model for Computation of Probabilistic Testability in Combinational Circuits. Integration, the VLSI Journal,1989,7(1): 49-75
[10]Roth J P, Bouricius W G, Schneider P R. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Transactions on Computers.1967,16(5):567-580
[11]C.W.Cha,W.E.Donath,and F.Ozguner,9-V Algorithm For Test Pattern Generation of Combinational Digital Circuits，IEEE Transactions on Computer. 1978,27(3):193-200
[12]P Muth.A Nine-Valued Circuit Model for Test Generation.IEEE Transactions on Computer.1976,25(6):630-636
[13]Goel P. An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Transactions on Computer.1981,30(3):215-222
[14]Fujiwara H and Shimono T. On the Acceleration of Test Generation Algorithms. IEEE Transactions on Computers,1983,32(12):1137-1144
[15]Hamzaoglum I and Patel J H. New Techniques for Deterministic Test Pattern Generation. In:Proc of IEEE VLSI Test Symposium. New Jersey,1998,446-452
[16]Hamzaoglum I and Patel J H. Test Set Compaction Algorithms for Combinational Circuits. In:Proc of IEEE International Conference on Computer-Aided Design. California,1998,283-289
[17]MIL-STD-2165A.Testability Program for Systems and Equipment. USA: Military Specifications and Standards,1993
[18]温熙森.可测试性技术的现状与未来.测控技术,2000,19(1)：9-12
[19]胡瑜,韩银和,李晓维.SOC可测试性设计与测试技术.计算机研究与发展,2005,42(1)：153-162
[20]Koenemann B, Mucha J, Zwiehoff G. Built-in Test for Complex Idgital Integrated Circuits. IEEE Journal of Solid-State Circuits, Vol.SC-15, no.3,2008,315-318
[21]Roth J P, Bouricius W G, and Schneider P R. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Transactions on Electronic Computers,1967,16(10):567-579
[22]IEEE(1994). Supplement(B) to IEEE Standard Test Access Port and Boundary-Scan Architecture. Http://ieeexplore.ieee.org/iel1/2860/5509/002112 26.pdf,1994-09-22
[23]蒋安平,冯建华,王新安等.超大规模集成电路测试-数字、存储器和混合信号系统.北京：电子工业出版社,2006,351
[24]Roy K and Prasad S. Low-power CMOS VLSI Circuit Design. New York:a Wiley Interscience Publication,2000,100-110
[25]Girard P. Survey of Low-Power Testing of VLSI Circuits. IEEE Design & Test of Computers,2000,19(3)：82-92
[26]S.Kajihara, A. Murakami, and T. Kaneko.On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits.In:Proc of Asian Tesr Symp,1999,20-21
[27]X. Lin, J. Rajski, I. Pomeranz, et al. On Static Test Compaction and Test Pattern Ordering for Scan Designs. In:Proc of Int'l Tesr Conf.2001,1088-1097
[28]Scan test data volume reduction in multi-clocked designs with safe capture technique," In:Proc of Int'l Tesr Conf.2002,148-153
[29]X. Lin and R. Thompson. Test generation for designs with multiple clocks.In:Proc of Design Aufomation Conf.2003,662-667
[30]B. Koeuemann. LFSR-Coded Test Patterns for Scan Designs. In:Proc of European Test Conf.1991,237-242
[31]B. Courtois. Built-in Test for Circuits with Scan Based Reseeding of Multiple Polynomial Linear Feedback Shift Registers.IEEE Transactions on Computers, 1995,44(2):223-233
[32]1. Rajski, J. Tysrer, M. Kassab, et al. Embedded Deterministic Test for Low Cost Manufacturing Test. In:Proc of Int'l Test Conf.2002,301-310
[33]P. Wohl, J. Waicukauski, S. Patel, et al. X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture. In:Proc of Inr'l Test Conf,2003,727-736
[34]Hamzaoglu I and Patel J. Reducing Test Application Time for Full Scan Embedded Cores. In:Proc of IEEE FTCS. Wisconsin,1999,260-267
[35]Pandey A R and Patel J. Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs. In:Proc of IEEE VLSI Test Symposium. Monterey,2002,9-15
[36]L.-T. Wang et al. VirtualScan:A New Compressed Scan Technology for Test Cost Reduction. In:Proc of Int'l TestConf. (ITC 04), IEEE CS Press,2004,916-925
[37]L.T. Wang, C.-W. Wu, X. Wen, VLSI Test Principles and Architectures, Morgan Kaufmann,2006
[38]R. Tekumalla. On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures.In:Proc of Int'l Test Conf.2003,737-744
[39]Touba, N.A. X-Canceling MISR-An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR. In:Proc of International Test Conference.2007,1-10
[40]Pouya B and Touba N A. Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. In:Proc of VTS. Princeton,1998,70-77
[41]Chakrabarty K. Zero-Aliasing Space Compaction Using Linear Compactors with Bounded Overhead. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1998,17(5):452-457
[42]S. Mitra, K. S. Kim. X-compact:An efficient response compaction technique for test cost reduction. In:Proc of Int'l Test Conf. Baltimore,2002
[43]S. Mitra, K. S. Kim. X-compact:An efficient response compaction technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.2004,23(3):421-432
[44]Chao M C T, Wang S, Chakradhar S T, et al. ChiYun Compact:A Novel Test Compaction Technique for Responses with Unknown Values. In:Proc of International Conference on Computer Design. San Jose,2005,147-152.
[45]J. Rajski, J. Tyszer, C. Wang and S. M. Reddy.Convolutional Compaction of Test Responses. In:Proc of IEEE International Test Conference.2003,745-754
[46]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski,et al.Fault Diagnosis in Designs with Convolutional Compactors. In Proc of IEEE International Test Conference. 2004,498-507
[47]Miyase K and Kajihara S. Optimal Scan Tree Construction with Test Vector Modification for Test Compression. In:Proc of IEEE Asian Test Symposium. Xian,2003,136-141
[48]Miyase K, Kajihara S and Reddy S M. Multiple Scan Tree Design with Test Vector Modification. In:Proc of IEEE Asian Test Symposium. Kenting,2004, 76-81
[49]Yotsuyanagi H, Kuchii T, Nishikawa S, et al. Reduce Scan Shifts Using Folding Scan Trees. In:Proc of IEEE Asian Test Symposium. Xian,2003,6-11
[50]Bonhomme Y, Yoneda T, Fujiwara H, et al. An Efficient Scan Tree Design for Test Time Reduction. In:Proc of IEEE European Test Symposium. Ajaccio,2004, 174-179
[51]Banerjee S, Chowdhury D. R, Bhattacharya B. An Efficient Scan Tree Design for Compact Test Pattern Set. IEEE Transactions On Computer-Aided Design of Intergrated Circuits and Systems,2007,26(7):1331-1339
[52]Xiang D, Gu S, Sun J. and Wu Y. A Cost-Effective Scan Architecture for Scan Testing with Nonscan Test Power and Test Application Cost. In:Proc of ACM/IEEE Design Automation Conference, California,2003,744-747
[53]You Z, Inoue M, Fujiwara H. Extended Compatibilities for Scan Tree Construction. In:Proc of IEEE European Test Symposium, Southampton, 2006,13-18
[54]Cheng Y, You Z and Kuang J. Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. In:Proc of IEEE International Symposium on Electronic Design, Test and Applications. Hong Kong,2008,308-313
[55]成永升,尤志强,邝继顺.扩展相容性扫描树中的测试响应压缩器设计.计算机辅助设计与图形学学报,2009,21(4)：500—504
[56]黄杰弟,尤志强,邝继顺,等.基于扩展相容性扫描树的响应压缩器设计.科技论文在线,论文编号：200903-301
[57]DaiG,You Z, KuangJ, et al. DCScan:A Power-Aware Scan Testing Architecture, In 17th Asian Test Symposium (ATS2008),2008,343-348
[58]Bonhomme Y, Girard P, Landrault C, et al. Power Driven Chaining of Flip-Flops in Scan Architecture. In:Proc of IEEE International Test Conference.Baltimore. 2002,796-803
[2]Paul H. B, Mcanney W. H, Savir J. Built-in Test for VLSI Pseudorandom Techniques. Wiley-Interscience. NY:1987,151-153
[3]Bennetts R. Design of Testable Logic Circuits. Addison-Wesley. London: 1984,74-77
[4]Timoc C, Buehler M L, Griswold T, et al. Logical Models of Physical Failures. In: Proc of International Test Conference. Philadelphia,1983,546-553
[5]Bushnell M L and Agrawal V D. Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits. USA:Kluwer Academic Publishers, 2000,13-14
[6]Miron Abramovici,Melvin A.Breuer,Arthur D.Friedman.数字系统的测试与可测性设计.北京：机械工业出版社,2006,87
[7]Goldstein L H and Thigpen E L. SCOAP:Sandia Controllability/Observability Analysis Program. In:Proc of the 17th Design Automation Conference. Las Vegas,1980,190-196
[8]Agrawal V D and Mercer M R. Testability Measures-What Do They Tell Us. In: Proc of International Test Conference. Philadelphia,1982,391-396
[9]Seth S C and Agrawal V D. A New Model for Computation of Probabilistic Testability in Combinational Circuits. Integration, the VLSI Journal,1989,7(1): 49-75
[10]Roth J P, Bouricius W G, Schneider P R. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Transactions on Computers.1967,16(5):567-580
[11]C.W.Cha,W.E.Donath,and F.Ozguner,9-V Algorithm For Test Pattern Generation of Combinational Digital Circuits，IEEE Transactions on Computer. 1978,27(3):193-200
[12]P Muth.A Nine-Valued Circuit Model for Test Generation.IEEE Transactions on Computer.1976,25(6):630-636
[13]Goel P. An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Transactions on Computer.1981,30(3):215-222
[14]Fujiwara H and Shimono T. On the Acceleration of Test Generation Algorithms. IEEE Transactions on Computers,1983,32(12):1137-1144
[15]Hamzaoglum I and Patel J H. New Techniques for Deterministic Test Pattern Generation. In:Proc of IEEE VLSI Test Symposium. New Jersey,1998,446-452
[16]Hamzaoglum I and Patel J H. Test Set Compaction Algorithms for Combinational Circuits. In:Proc of IEEE International Conference on Computer-Aided Design. California,1998,283-289
[17]MIL-STD-2165A.Testability Program for Systems and Equipment. USA: Military Specifications and Standards,1993
[18]温熙森.可测试性技术的现状与未来.测控技术,2000,19(1)：9-12
[19]胡瑜,韩银和,李晓维.SOC可测试性设计与测试技术.计算机研究与发展,2005,42(1)：153-162
[20]Koenemann B, Mucha J, Zwiehoff G. Built-in Test for Complex Idgital Integrated Circuits. IEEE Journal of Solid-State Circuits, Vol.SC-15, no.3,2008,315-318
[21]Roth J P, Bouricius W G, and Schneider P R. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Transactions on Electronic Computers,1967,16(10):567-579
[22]IEEE(1994). Supplement(B) to IEEE Standard Test Access Port and Boundary-Scan Architecture. Http://ieeexplore.ieee.org/iel1/2860/5509/002112 26.pdf,1994-09-22
[23]蒋安平,冯建华,王新安等.超大规模集成电路测试-数字、存储器和混合信号系统.北京：电子工业出版社,2006,351
[24]Roy K and Prasad S. Low-power CMOS VLSI Circuit Design. New York:a Wiley Interscience Publication,2000,100-110
[25]Girard P. Survey of Low-Power Testing of VLSI Circuits. IEEE Design & Test of Computers,2000,19(3)：82-92
[26]S.Kajihara, A. Murakami, and T. Kaneko.On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits.In:Proc of Asian Tesr Symp,1999,20-21
[27]X. Lin, J. Rajski, I. Pomeranz, et al. On Static Test Compaction and Test Pattern Ordering for Scan Designs. In:Proc of Int'l Tesr Conf.2001,1088-1097
[28]Scan test data volume reduction in multi-clocked designs with safe capture technique," In:Proc of Int'l Tesr Conf.2002,148-153
[29]X. Lin and R. Thompson. Test generation for designs with multiple clocks.In:Proc of Design Aufomation Conf.2003,662-667
[30]B. Koeuemann. LFSR-Coded Test Patterns for Scan Designs. In:Proc of European Test Conf.1991,237-242
[31]B. Courtois. Built-in Test for Circuits with Scan Based Reseeding of Multiple Polynomial Linear Feedback Shift Registers.IEEE Transactions on Computers, 1995,44(2):223-233
[32]1. Rajski, J. Tysrer, M. Kassab, et al. Embedded Deterministic Test for Low Cost Manufacturing Test. In:Proc of Int'l Test Conf.2002,301-310
[33]P. Wohl, J. Waicukauski, S. Patel, et al. X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture. In:Proc of Inr'l Test Conf,2003,727-736
[34]Hamzaoglu I and Patel J. Reducing Test Application Time for Full Scan Embedded Cores. In:Proc of IEEE FTCS. Wisconsin,1999,260-267
[35]Pandey A R and Patel J. Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs. In:Proc of IEEE VLSI Test Symposium. Monterey,2002,9-15
[36]L.-T. Wang et al. VirtualScan:A New Compressed Scan Technology for Test Cost Reduction. In:Proc of Int'l TestConf. (ITC 04), IEEE CS Press,2004,916-925
[37]L.T. Wang, C.-W. Wu, X. Wen, VLSI Test Principles and Architectures, Morgan Kaufmann,2006
[38]R. Tekumalla. On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures.In:Proc of Int'l Test Conf.2003,737-744
[39]Touba, N.A. X-Canceling MISR-An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR. In:Proc of International Test Conference.2007,1-10
[40]Pouya B and Touba N A. Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. In:Proc of VTS. Princeton,1998,70-77
[41]Chakrabarty K. Zero-Aliasing Space Compaction Using Linear Compactors with Bounded Overhead. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1998,17(5):452-457
[42]S. Mitra, K. S. Kim. X-compact:An efficient response compaction technique for test cost reduction. In:Proc of Int'l Test Conf. Baltimore,2002
[43]S. Mitra, K. S. Kim. X-compact:An efficient response compaction technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.2004,23(3):421-432
[44]Chao M C T, Wang S, Chakradhar S T, et al. ChiYun Compact:A Novel Test Compaction Technique for Responses with Unknown Values. In:Proc of International Conference on Computer Design. San Jose,2005,147-152.
[45]J. Rajski, J. Tyszer, C. Wang and S. M. Reddy.Convolutional Compaction of Test Responses. In:Proc of IEEE International Test Conference.2003,745-754
[46]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski,et al.Fault Diagnosis in Designs with Convolutional Compactors. In Proc of IEEE International Test Conference. 2004,498-507
[47]Miyase K and Kajihara S. Optimal Scan Tree Construction with Test Vector Modification for Test Compression. In:Proc of IEEE Asian Test Symposium. Xian,2003,136-141
[48]Miyase K, Kajihara S and Reddy S M. Multiple Scan Tree Design with Test Vector Modification. In:Proc of IEEE Asian Test Symposium. Kenting,2004, 76-81
[49]Yotsuyanagi H, Kuchii T, Nishikawa S, et al. Reduce Scan Shifts Using Folding Scan Trees. In:Proc of IEEE Asian Test Symposium. Xian,2003,6-11
[50]Bonhomme Y, Yoneda T, Fujiwara H, et al. An Efficient Scan Tree Design for Test Time Reduction. In:Proc of IEEE European Test Symposium. Ajaccio,2004, 174-179
[51]Banerjee S, Chowdhury D. R, Bhattacharya B. An Efficient Scan Tree Design for Compact Test Pattern Set. IEEE Transactions On Computer-Aided Design of Intergrated Circuits and Systems,2007,26(7):1331-1339
[52]Xiang D, Gu S, Sun J. and Wu Y. A Cost-Effective Scan Architecture for Scan Testing with Nonscan Test Power and Test Application Cost. In:Proc of ACM/IEEE Design Automation Conference, California,2003,744-747
[53]You Z, Inoue M, Fujiwara H. Extended Compatibilities for Scan Tree Construction. In:Proc of IEEE European Test Symposium, Southampton, 2006,13-18
[54]Cheng Y, You Z and Kuang J. Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. In:Proc of IEEE International Symposium on Electronic Design, Test and Applications. Hong Kong,2008,308-313
[55]成永升,尤志强,邝继顺.扩展相容性扫描树中的测试响应压缩器设计.计算机辅助设计与图形学学报,2009,21(4)：500—504
[56]黄杰弟,尤志强,邝继顺,等.基于扩展相容性扫描树的响应压缩器设计.科技论文在线,论文编号：200903-301
[57]DaiG,You Z, KuangJ, et al. DCScan:A Power-Aware Scan Testing Architecture, In 17th Asian Test Symposium (ATS2008),2008,343-348
[58]Bonhomme Y, Girard P, Landrault C, et al. Power Driven Chaining of Flip-Flops in Scan Architecture. In:Proc of IEEE International Test Conference.Baltimore. 2002,796-803