集成电路设计中乘法器的低功耗算法与实现技术研究
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摘要
近年来，随着集成电路设计技术的高速发展，功耗已经成为该领域中除速度、面积之外需要考虑的第三因素。如今低功耗设计从电路基本组成因素出发，在设计的各个阶段采用不同的设计以降低系统功耗，以取得最大限度的低功耗效果。本文紧跟市场发展动向，从以上应用角度出发，着力研究集成电路设计中小数乘法器的前端低功耗算法以及实现技术，并且改进了现有低功耗设计技术的一些不足之处。研究成果包括：
（1）针对乘法器内部加法运算次数的优化
提出一种针对定点乘法系数的编码方式，使得重新编码后的系数所含非零位最少，以此来优化乘法器内部加法运算的次数。由于该算法不需要降低系统工作时钟频率和工作电压，而是直接减少了各乘法器中加法运算的数量，因此不会降低系统工作效率；由于该算法从优化乘法器内部加法结构入手，没有引入任何的近似运算，因此不损失乘法运算精度。为了测试该算法的实际低功耗效果，文章对含有大量各种不同类型乘法器的上层应用系统进行优化，然后对优化后的系统进行功耗分析和硬件测试，测试结果为该算法对各种不同类型小数乘法器进行优化的平均结果，更具有客观性、一般性和实际参考价值。
（2）针对乘法器内部各级加法运算结果位宽的优化
通过对小数乘法运算的误差分析，推导出一种针对定点小数乘法器的优化算法，其能够在保证小数乘法器运算精度的前提下，减少其内部总寄存器位宽。该算法在定点小数乘法器内部各级加法结果中，预先计算出在最终运算结果中将要被缺省掉的数据末位，直接在各级结果中缺省，以此来减小乘法器的总位宽。由于该算法缺省掉的是本应在最终结果中缺省的数位，因此不会对小数乘法运算产生额外的误差；由于该算法只需搜索乘法器系数中“1”的排列和位置进而进行右移缺省操作，因此其具有运行速度快，占用资源少，简单易行的特点。文章对小数乘法器优化后，进一步对其上层应用系统，插值滤波器进行优化，优化后滤波器的工作特性基本没有发生变化，但所含逻辑单元数明显减少。接下来，更进一步对含有一些数字处理模块（例如滤波器、混频器、DSP等）的射频电路进行优化，优化后射频电路的功耗分析与硬件测试结果均取得了期望的效果。文章逐步给出了该算法由底层到高层的具体开发过程，具有实际参考意义。
（3）双重优化算法
基于以上两种优化算法，文章提出一种可以同时优化乘法器内部加法运算次数与各级加法运算结果位宽的，具有双重优化作用的低功耗算法。该算法先对乘法系数进行优化编码，以此来减少乘法器内部加法器的数量，再根据优化后的系数在各级加法结果中计算并且直接缺省掉本应在最终结果中缺省掉的数据末位，以此来优化乘法器总位宽。在算法实现上，保存第一次优化的运算结果，为第二次优化所用，大量节省了第二次优化的计算量，提高算法整体运算速度和工作效率。双重优化算法使得两种不同算法具有良好的匹配性，相比于二者的直接结合具有更高的工作效率以及更优的实际低功耗效果。
（4）算法的实现技术
文章针对现阶段低功耗设计中优化逻辑自身的功耗和面积进入被优化系统从而抵消系统整体优化效果的问题，提出了一种全新的实现技术，使得优化后的乘法器具有优化算法的低功耗效果，同时又避免引入算法自身的逻辑单元。对于含有乘法器的系统，系统的参数和特性一旦确定，其内部各乘法器系数也将确定。因此在乘法器综合之前根据已经确定的系数进行优化运算，再以优化后的系数参与各级加法运算并进行缺省操作，这样可以避免优化算法自身的逻辑单元引入优化后的乘法器。在算法实现级，该技术进一步提升了优化算法的实际低功耗效果，并且改进了现阶段低功耗设计中的问题。
（5）系统级低功耗设计技术
基于前面得出的最优算法和实现技术，在系统应用层面，针对系统内部各种不同类型的乘法器，选取与之匹配的优化算法和硬件实现结构，进一步进行优化。在算法选取上，对于整数系数乘法器，优化其内部加法运算次数；对于系数小于1的小数乘法器，进行双重优化；对于系数大于1的小数乘法器，将整数部分和小数部分分别进行以上两种优化。在硬件实现结构的选取上，大量的实验结果表明，乘法系数中所含“1”的个数不大于4时，采用串联累加结构；反之则采用循环累加结构。系统级优化技术使得乘法器的低功耗效果得到进一步提升。
通过本文对集成电路设计领域中乘法器低功耗设计技术的研究，在算法上给出了针对其内部加法运算数量以及加法结果位宽的优化算法；在实现上给出了一种全新的实现技术，能够改进现阶段低功耗设计中存在问题；在系统应用上给出了不同优化算法和硬件实现结构的匹配技术。本文对集成电路前端设计领域中乘法器在不同层面所进行低功耗设计具有一定的参考和借鉴意义。
With rapid development of IC technologies, power consumption has been a keyfactor for long time, beside speed and area. Currently, low power design is developedfrom basic circuit constitution, try to reduce system power consumption in each stage ofIC manufactory flow, in order to obtain the optimal low power result. The dissertationfollows to such tendency, and focuses to research and design low power methodologyand implementation, at meanwhile, improve some shortages of current low powerdesign. The main work and innovations of this dissertation are as follows:
(1) Optimization for the number of addition operation inside multiplier
Develop an encoding methodology for fixed multiplication coefficient, its major isto minimum non-zero bits in optimized coefficient, in order to reduce the number ofaddition operations, which are inside multiplier. Since the methodology reducesaddition operation, rather than decrease system clock frequency and supply voltage, soit does not reduce system efficiency. And, the methodology optimizes internal structureof mulriplier, does not involve any approximation, so it does not cause anymultiplication accuracy loss. In order to test the actual low power effect, a system thatincludes several knids of multipliers is to be the optimization object, the test result is theaverage optimization result of all the intern multipliers, so it is objective, general andactual.
(2) Optimization for the width of decimal multiplier
After error analysis to decimal multiplier, an optimization methodology for decimalmultiplier is developed, its major is reducing the total register bits with maintaining itsoperation accuracy. The methodology can pre-calculate the last-significant-bits in eachaddition operations and omit them directly, these bits will be omited in final calculationresult, so that total register bits of multiplier can be reduced. Because the methodologyonly omit the so call “last-significant-bits”, so it does not cause more calculation error.And it only search all the “1” in coefficient and then excute further operation, so themethodology has advantages of high speed, little resource occupy and easy toimplement. In order to test the actual low power effect of such methodology, aninterpolation filter is optimized by it, its internal logic cells are reduced significantlywithout working characteristics deterioration. Then, a RF circuit is treated as theoptimization object, its optimization result is also meet our expectation. The chapter describe the methodology development from singal multiplier to RF circuit, it has actualreference value.
(3) Dual optimization methodology
Base on the2methodologies, a dual optimization methodology is developed, itreduces not only the number of addition operations, but also the width of one multiplier.Firstly, the methodology reduces the number of addition operations, then based on suchoptimization result, it reduces width of each addition once again. From implementationpoint of view, the result of first optimization can be used for the second one, suchimplementation save the computation effort of second optimization, and promoteoperation speed and efficiency of whole methodology. Compared to directly binding oftwo single methodologies, dual methodology has higher working efficiency, and betterlow power result.
(4) Implementation solution
To improve the problem of optimization logic is brought into optimized system,which is existed in present low power design, the dissertation develop a newimplementation technique. By using it, the optimized system has expected low powerresult, at meanwhile, the optimization logic cells are absented in it. For the system thatinclude multipliers, once its characteristics is confirmed, the coefficients of all theinternal multipliers are also fixed, so each coefficient can be optimized in advance, then,the operation is excuted just based on the optimized coefficient after synthesis, thissolution avoid optimized multiplier to include optimization logic cells. Fromsystempoint of view, such solution promote the actual result of methodology.
(5) System level low power optimization approach
On system level, based on dual optimization methododlogy and newimplementation solution, plus select different software methodologies and hardwarestructures for different kinds of multiplier. In optimization methododlogy stage, additionnumber optimization is for integer multiplier, dual optimization is for decimal multiplierwhose coefficient is less than one, separately optimization to the integer and decimalparts of decimal multiplier whose coefficient is larger than one. In hardware structurestatge, use series accumulate structure when the count of one in the coefficient is nomore than four, otherwise use cycle accumulate structure. Such approach is system levellow power approach, it promotes system low power result.
Through the research of low power technique for multipliers in IC design, inmethodology stage, optimization for addition number and addition width are developed, in implementation stage, a new implementation solution is developed, which canimprove the problem of present low power design, in system application stage, amemthodology and structure selection is developed. The dissertation develop the lowpower technique for multipliers in different stages, it has reference value to IC front-endlow power design for fixed coefficient multipliers.
（1）针对乘法器内部加法运算次数的优化
提出一种针对定点乘法系数的编码方式，使得重新编码后的系数所含非零位最少，以此来优化乘法器内部加法运算的次数。由于该算法不需要降低系统工作时钟频率和工作电压，而是直接减少了各乘法器中加法运算的数量，因此不会降低系统工作效率；由于该算法从优化乘法器内部加法结构入手，没有引入任何的近似运算，因此不损失乘法运算精度。为了测试该算法的实际低功耗效果，文章对含有大量各种不同类型乘法器的上层应用系统进行优化，然后对优化后的系统进行功耗分析和硬件测试，测试结果为该算法对各种不同类型小数乘法器进行优化的平均结果，更具有客观性、一般性和实际参考价值。
（2）针对乘法器内部各级加法运算结果位宽的优化
通过对小数乘法运算的误差分析，推导出一种针对定点小数乘法器的优化算法，其能够在保证小数乘法器运算精度的前提下，减少其内部总寄存器位宽。该算法在定点小数乘法器内部各级加法结果中，预先计算出在最终运算结果中将要被缺省掉的数据末位，直接在各级结果中缺省，以此来减小乘法器的总位宽。由于该算法缺省掉的是本应在最终结果中缺省的数位，因此不会对小数乘法运算产生额外的误差；由于该算法只需搜索乘法器系数中“1”的排列和位置进而进行右移缺省操作，因此其具有运行速度快，占用资源少，简单易行的特点。文章对小数乘法器优化后，进一步对其上层应用系统，插值滤波器进行优化，优化后滤波器的工作特性基本没有发生变化，但所含逻辑单元数明显减少。接下来，更进一步对含有一些数字处理模块（例如滤波器、混频器、DSP等）的射频电路进行优化，优化后射频电路的功耗分析与硬件测试结果均取得了期望的效果。文章逐步给出了该算法由底层到高层的具体开发过程，具有实际参考意义。
（3）双重优化算法
基于以上两种优化算法，文章提出一种可以同时优化乘法器内部加法运算次数与各级加法运算结果位宽的，具有双重优化作用的低功耗算法。该算法先对乘法系数进行优化编码，以此来减少乘法器内部加法器的数量，再根据优化后的系数在各级加法结果中计算并且直接缺省掉本应在最终结果中缺省掉的数据末位，以此来优化乘法器总位宽。在算法实现上，保存第一次优化的运算结果，为第二次优化所用，大量节省了第二次优化的计算量，提高算法整体运算速度和工作效率。双重优化算法使得两种不同算法具有良好的匹配性，相比于二者的直接结合具有更高的工作效率以及更优的实际低功耗效果。
（4）算法的实现技术
文章针对现阶段低功耗设计中优化逻辑自身的功耗和面积进入被优化系统从而抵消系统整体优化效果的问题，提出了一种全新的实现技术，使得优化后的乘法器具有优化算法的低功耗效果，同时又避免引入算法自身的逻辑单元。对于含有乘法器的系统，系统的参数和特性一旦确定，其内部各乘法器系数也将确定。因此在乘法器综合之前根据已经确定的系数进行优化运算，再以优化后的系数参与各级加法运算并进行缺省操作，这样可以避免优化算法自身的逻辑单元引入优化后的乘法器。在算法实现级，该技术进一步提升了优化算法的实际低功耗效果，并且改进了现阶段低功耗设计中的问题。
（5）系统级低功耗设计技术
基于前面得出的最优算法和实现技术，在系统应用层面，针对系统内部各种不同类型的乘法器，选取与之匹配的优化算法和硬件实现结构，进一步进行优化。在算法选取上，对于整数系数乘法器，优化其内部加法运算次数；对于系数小于1的小数乘法器，进行双重优化；对于系数大于1的小数乘法器，将整数部分和小数部分分别进行以上两种优化。在硬件实现结构的选取上，大量的实验结果表明，乘法系数中所含“1”的个数不大于4时，采用串联累加结构；反之则采用循环累加结构。系统级优化技术使得乘法器的低功耗效果得到进一步提升。
通过本文对集成电路设计领域中乘法器低功耗设计技术的研究，在算法上给出了针对其内部加法运算数量以及加法结果位宽的优化算法；在实现上给出了一种全新的实现技术，能够改进现阶段低功耗设计中存在问题；在系统应用上给出了不同优化算法和硬件实现结构的匹配技术。本文对集成电路前端设计领域中乘法器在不同层面所进行低功耗设计具有一定的参考和借鉴意义。
With rapid development of IC technologies, power consumption has been a keyfactor for long time, beside speed and area. Currently, low power design is developedfrom basic circuit constitution, try to reduce system power consumption in each stage ofIC manufactory flow, in order to obtain the optimal low power result. The dissertationfollows to such tendency, and focuses to research and design low power methodologyand implementation, at meanwhile, improve some shortages of current low powerdesign. The main work and innovations of this dissertation are as follows:
(1) Optimization for the number of addition operation inside multiplier
Develop an encoding methodology for fixed multiplication coefficient, its major isto minimum non-zero bits in optimized coefficient, in order to reduce the number ofaddition operations, which are inside multiplier. Since the methodology reducesaddition operation, rather than decrease system clock frequency and supply voltage, soit does not reduce system efficiency. And, the methodology optimizes internal structureof mulriplier, does not involve any approximation, so it does not cause anymultiplication accuracy loss. In order to test the actual low power effect, a system thatincludes several knids of multipliers is to be the optimization object, the test result is theaverage optimization result of all the intern multipliers, so it is objective, general andactual.
(2) Optimization for the width of decimal multiplier
After error analysis to decimal multiplier, an optimization methodology for decimalmultiplier is developed, its major is reducing the total register bits with maintaining itsoperation accuracy. The methodology can pre-calculate the last-significant-bits in eachaddition operations and omit them directly, these bits will be omited in final calculationresult, so that total register bits of multiplier can be reduced. Because the methodologyonly omit the so call “last-significant-bits”, so it does not cause more calculation error.And it only search all the “1” in coefficient and then excute further operation, so themethodology has advantages of high speed, little resource occupy and easy toimplement. In order to test the actual low power effect of such methodology, aninterpolation filter is optimized by it, its internal logic cells are reduced significantlywithout working characteristics deterioration. Then, a RF circuit is treated as theoptimization object, its optimization result is also meet our expectation. The chapter describe the methodology development from singal multiplier to RF circuit, it has actualreference value.
(3) Dual optimization methodology
Base on the2methodologies, a dual optimization methodology is developed, itreduces not only the number of addition operations, but also the width of one multiplier.Firstly, the methodology reduces the number of addition operations, then based on suchoptimization result, it reduces width of each addition once again. From implementationpoint of view, the result of first optimization can be used for the second one, suchimplementation save the computation effort of second optimization, and promoteoperation speed and efficiency of whole methodology. Compared to directly binding oftwo single methodologies, dual methodology has higher working efficiency, and betterlow power result.
(4) Implementation solution
To improve the problem of optimization logic is brought into optimized system,which is existed in present low power design, the dissertation develop a newimplementation technique. By using it, the optimized system has expected low powerresult, at meanwhile, the optimization logic cells are absented in it. For the system thatinclude multipliers, once its characteristics is confirmed, the coefficients of all theinternal multipliers are also fixed, so each coefficient can be optimized in advance, then,the operation is excuted just based on the optimized coefficient after synthesis, thissolution avoid optimized multiplier to include optimization logic cells. Fromsystempoint of view, such solution promote the actual result of methodology.
(5) System level low power optimization approach
On system level, based on dual optimization methododlogy and newimplementation solution, plus select different software methodologies and hardwarestructures for different kinds of multiplier. In optimization methododlogy stage, additionnumber optimization is for integer multiplier, dual optimization is for decimal multiplierwhose coefficient is less than one, separately optimization to the integer and decimalparts of decimal multiplier whose coefficient is larger than one. In hardware structurestatge, use series accumulate structure when the count of one in the coefficient is nomore than four, otherwise use cycle accumulate structure. Such approach is system levellow power approach, it promotes system low power result.
Through the research of low power technique for multipliers in IC design, inmethodology stage, optimization for addition number and addition width are developed, in implementation stage, a new implementation solution is developed, which canimprove the problem of present low power design, in system application stage, amemthodology and structure selection is developed. The dissertation develop the lowpower technique for multipliers in different stages, it has reference value to IC front-endlow power design for fixed coefficient multipliers.
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