SoC芯片的低功耗物理设计研究
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摘要
随着半导体工艺的迅猛发展,设计规模和集成度不断提高,集成电路(IC,integrated circuit)已进入了SoC(system on chip)时代。然后功耗却是SoC设计的一个瓶颈问题,它已成为与面积和性能同等重要的设计目标。因此低功耗设计已成为SoC设计最严峻的挑战之一。
本文主要研究了一款SoC芯片低功耗设计方法。设计目的是在保证性能的前提下,达到很低的功耗要求。为了达到低SoC芯片的功耗设计要求,本文从芯片布局规划、门控时钟插入以及时钟网络设计三个方面加以研究。
首先,论文从布局规划着手。提出了具有多芯片封装结构的SoC芯片的合理布局方法,包括芯片面积的确定,输入输出管脚(IO Pad)、IP(intellectual property)硬核放置规划;同时论文提出了一种针对多金属层芯片设计的电源网络设计方法,该方法以较少的布线资源实现了电源的充分连接,为芯片的后期布局布线提供了更充足的布线资源。其次,论文通过模块间以及模块内部门控时钟的合理插入实现了芯片功耗的动态管理,从而保证低功耗设计的要求。最后,论文通过对现有时钟网络结构的分析,提出两种时钟网络设计方案:一种是改进的时钟网格(mesh)+局部树(local tree)MLT结构的设计方法——时钟网格(mesh)+局部树自动综合(local tree auto synthesis)MLTAS设计,该方法能够有效的减少缓冲器数量,减小时钟偏差;另一种是低功耗时钟树综合(LPCTS low power clock tree synthesis),该方法能够缩短设计周期。将两种方法加以对比,最终选择LPCTS作为芯片低功耗设计更为合理的时钟网络设计方法。
本论文研究的SoC芯片采用0.18um工艺,具有6层布线金属层,并基于标准单元的设计模式进行设计,运用Cadence公司的Encounter工具加以实现。通过对芯片进行了电压降(IR Drop)和功耗的仿真分析,验证了功耗的完整性,满足了低功耗设计的要求。最后将仿真与实测结果进行对比,验证了芯片设计的正确性。
With the fast development of the technics of semiconductor, the scale of design and integration is becoming more and more higher, Integrated circuits has entered the SoC (system on chip) era. However, the power comsumption is the bottle-neck problem of the SoC design, and becomes the same important design target as the acreage and performance. So the low-power design has became one of the serious challenge of SoC design.
The dissertion researches the methods of the low-power design of a SoC chip. The purpose of designing the chip is to gain the much lower power on condition that the performance of the chip is right. In order to reach the the require of low-power design, the dissertion reseaches the three aspects below, which are acreage optimization, clock gating insertion, clock network design.
Firstly, focusing on Floorplan, the dissertation raises a reasonable method for the SoC chip with the multi-chip encapsulation structure, which contains the decision of the acreage and the floorplan of IO pad, IP core and standard cells. At the same time the dissertation raises a clock-network design method for the multi-metal-floor design. The method can connect the power sufficiently under the little routing resource and provide a sufficient routing resource for the next placing and routing. Secondly, we reasonablely use the clock-gating insertion method for the design which is putting the clock gating between the modules and standard cells of a module to realize dynamic power management. It makes sure the require of the low power. Finally, analysing the existed structure of the clock network, the dissertation provides two schemes for this design. One is a advanced design method named MLTAS(mesh+local tree auto synthesis) which bases on the MLT(mesh+local tree) structure and can effectively reduce the numbers of the buffer and the clock skew, while the other is LPCTS(low power clock tree synthesis) that can reduce the design period. Comparing the two methods, we choose the LPCTS as the more suitable clock-network design method for the low power design at last.
The research SoC chip of the dissertion is designed with the Encounter tool of Cadence, which employs the 0.18um process with the six-floors metal and bases the standard-cells’design mode. Then the dissertion does the emulational analysis for the IR Drop and power. So the power integrality is validated and the require of low-power design is satisfied. Lastly, it contrastively analyses the emulational result and the actual testing result of the SoC chip, which validates the correctness of the chip design.
本文主要研究了一款SoC芯片低功耗设计方法。设计目的是在保证性能的前提下,达到很低的功耗要求。为了达到低SoC芯片的功耗设计要求,本文从芯片布局规划、门控时钟插入以及时钟网络设计三个方面加以研究。
首先,论文从布局规划着手。提出了具有多芯片封装结构的SoC芯片的合理布局方法,包括芯片面积的确定,输入输出管脚(IO Pad)、IP(intellectual property)硬核放置规划;同时论文提出了一种针对多金属层芯片设计的电源网络设计方法,该方法以较少的布线资源实现了电源的充分连接,为芯片的后期布局布线提供了更充足的布线资源。其次,论文通过模块间以及模块内部门控时钟的合理插入实现了芯片功耗的动态管理,从而保证低功耗设计的要求。最后,论文通过对现有时钟网络结构的分析,提出两种时钟网络设计方案:一种是改进的时钟网格(mesh)+局部树(local tree)MLT结构的设计方法——时钟网格(mesh)+局部树自动综合(local tree auto synthesis)MLTAS设计,该方法能够有效的减少缓冲器数量,减小时钟偏差;另一种是低功耗时钟树综合(LPCTS low power clock tree synthesis),该方法能够缩短设计周期。将两种方法加以对比,最终选择LPCTS作为芯片低功耗设计更为合理的时钟网络设计方法。
本论文研究的SoC芯片采用0.18um工艺,具有6层布线金属层,并基于标准单元的设计模式进行设计,运用Cadence公司的Encounter工具加以实现。通过对芯片进行了电压降(IR Drop)和功耗的仿真分析,验证了功耗的完整性,满足了低功耗设计的要求。最后将仿真与实测结果进行对比,验证了芯片设计的正确性。
With the fast development of the technics of semiconductor, the scale of design and integration is becoming more and more higher, Integrated circuits has entered the SoC (system on chip) era. However, the power comsumption is the bottle-neck problem of the SoC design, and becomes the same important design target as the acreage and performance. So the low-power design has became one of the serious challenge of SoC design.
The dissertion researches the methods of the low-power design of a SoC chip. The purpose of designing the chip is to gain the much lower power on condition that the performance of the chip is right. In order to reach the the require of low-power design, the dissertion reseaches the three aspects below, which are acreage optimization, clock gating insertion, clock network design.
Firstly, focusing on Floorplan, the dissertation raises a reasonable method for the SoC chip with the multi-chip encapsulation structure, which contains the decision of the acreage and the floorplan of IO pad, IP core and standard cells. At the same time the dissertation raises a clock-network design method for the multi-metal-floor design. The method can connect the power sufficiently under the little routing resource and provide a sufficient routing resource for the next placing and routing. Secondly, we reasonablely use the clock-gating insertion method for the design which is putting the clock gating between the modules and standard cells of a module to realize dynamic power management. It makes sure the require of the low power. Finally, analysing the existed structure of the clock network, the dissertation provides two schemes for this design. One is a advanced design method named MLTAS(mesh+local tree auto synthesis) which bases on the MLT(mesh+local tree) structure and can effectively reduce the numbers of the buffer and the clock skew, while the other is LPCTS(low power clock tree synthesis) that can reduce the design period. Comparing the two methods, we choose the LPCTS as the more suitable clock-network design method for the low power design at last.
The research SoC chip of the dissertion is designed with the Encounter tool of Cadence, which employs the 0.18um process with the six-floors metal and bases the standard-cells’design mode. Then the dissertion does the emulational analysis for the IR Drop and power. So the power integrality is validated and the require of low-power design is satisfied. Lastly, it contrastively analyses the emulational result and the actual testing result of the SoC chip, which validates the correctness of the chip design.
引文
[1]懂文萧.片上网络低功耗设计研究[D].浙江大学博士学历论文,2010: 1-10.
[2]催义智.低功耗技术在后端设计中的应用[D].复旦大学硕士学位论文,2008: 1-30.
[3] M.Keating, P.Bricaud. Reuse Methodology Manual for System-On-Chip Design. Boston/Dorecht/London: Kluwer[M]. Academic Publishers, 2000.
[4]唐杉,徐强,王莉薇.数字IC设计[M].机械工业出版社,2006 :59-62.
[5]魏敬和,吴晓洁,虞致. SoC低功耗设计及其技术实现[J].电子与封装,2009,9(5): 20-23.
[6]张富彬, HO Ching-Yen,彭思龙. SoC设计中的低功耗策略[J].电子器件,2007,30(4): 633-636.
[7]王延升,刘雷波. SoC设计中的时钟低功耗技术[J].计算机工程,2009,35(24): 257-261.
[8] Donno M, Macii E, Mazzoni L. Power-Aware Clock Tree Planning[A]. Proc of ISPD’04[C]. 2004: 138-147.
[9]赵丽莎,罗胜钦. SOC技术及系统级低功耗设计[J].电子与封装,2008,8(9): 27-32.
[10]郭小川.低功耗物理设计[D].复旦大学硕士学位论文,2007: 19-25.
[11]陈静华. SoC芯片低功耗设计[D].湖南大学硕士学位论文,2005: 1-25.
[12] Chandrakasan, S. Sheng, R. Brodersen.Low-Power CMOS Digital Design[J]. IEEE Jounral of Solid State Cireuits, 1992, 27(4): 473-484.
[13] Chandrakasnan, R. Brodersen. Minimizing Power ConsumPtionin Digital CMOS Circuits[J]. Proceedings of the IEEE, 1995, 83(4): 495-523.
[14] Kaushik Roy, Sharat Prasad. Low Power CMOS VLSI Cireuit Design[M]. NewYork: A Wiley Interseience Publication, 2000, 5-43.
[15] Siva Narendra, Vivek De, Shekhar Borkar, et al. Full-Chip Subthreshold Leakage Power Prediction and Reduetion Techniquesfor Sub 0.18um CMOS[J]. IEEE Journal of Solid-State Circuits, 2004, 39(3): 131-139.
[16] Dongwoo Lee,David Blaauw, Dennis Sylvester. Gate Oxide Leakage Current Analysis and Reduction of VLSI Circuits[J]. IEEE Tran. On VLSI System, 2004, 12(2): 155-166.
[17] K. Roy, S. Mukhopadhyay, H. Mahmoodl. Leakage current mechanisms and leakage reduction teehniques in deep-submicrometer CMOS circuits[J]. Proceedings of the IEEE, 2003, 91(2): 305-327.
[18]黄伟坚.全芯片时钟网络的综合与优化方法[D].上海交通大学硕士学位论文,2010: 1-20.
[19]刘祥远,陈书明.高性能VLSI设计中时钟分布网络的问题与解决方法[J].计算机工程与科学,2007,29(6): 89-92.
[20] Alice Wang, Anantha P. Chandrakasan, Staphen V. Kosonocky, Optimal and Threshold Scaling for Subthreshold CMOS Circuits[J]. IEEE Computer Society Annual Symposium on VLSI, 2002.
[21] Jan M.Rabacy.数字集成电路设计与透视[M].清华大学出版社,1992.
[22] J.Cong, L.he, C.K.Koh, P.H.Madden. Performance Optimization of VLSI Interconnection Layout[J]. Integration, the VLSI Jounaral, 1996: 5-95.
[23]周凤亭.基于PC+ASTRO的深亚微米布局布线流程研究[D].东南大学硕士学位论文,2005: 1-40.
[24]咸德勇.深亚微米SoC的逻辑综合与版图设计[D].国防科大硕士学位论文,2006: 10-40.
[25] Hsiao-Pin Su, Youn-Long Lin. A timing-driven Soft-macro Placement and Resynthesis Method in Interaction with Chip Floorplanning [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999, 18(4): 475-483.
[26] Roy K, Prasad S. Low Power CMOS VLSI Circuit Design [M]. New York: A Wiley Interscience Publication, 2000.
[27]曾璇,周丽丽,黄晟,周电,李威.时钟延时及偏差最小化的缓冲器插入新算法[J].电子学报,2001,29(11): 1458-1462.
[28] YEH C, WILKE G, CHEN H. Clock distribution architecture: a comparative study[C]. Proc of the Int Symp on Quality Electronic Design. San Jose, CA, USA , 2006: 85-91.
[29] WILKE G R, MURGAI R. Design and analysis of“Tree +Local Meshes”clock architecture[C]. Proc of the Int Symp on Quality Electronic Design. San Jose, CA, USA, 2007: 165-170.
[30]马光胜,冯刚. SoC设计与IP核重用技术[M].国防工业出版社,2006.
[31] Cadence. RTL Compiler Manul[K], Version 7.1. 2007.
[32]郭小川.低功耗物理设计[D].复旦大学硕士学位论文,2007: 19-25.
[33]王彬,任艳颖.数字IC系统设计[J].西安电子科技大学. 2005:207-214.
[34]王超.语音SoC芯片数字后端低功耗研究[D].哈尔滨工业大学硕士学位论文,2010: 1-50.
[35]张宇弘.行为逻辑层上的SoC低功耗设计[D].浙江大学博士学位论文,2004: 1-15.
[36]郭炜,郭筝,谢憬. SoC设计方法与实现[M].电子工业出版社,2007.
[37]陈春章,艾霞,王国雄.数字集成电路物理设计[M].科学出版社,2008.
[38] Patnekar S S. High-performance power grids for nanometer technologies[J]. Proceedings of 17th International Conference on VLSI Design. 2004: 839-844.
[39] Zion Cien Shen, Chris C. N. Chu. Bounds on the Number of Slicing, Mosaic, and Genernal Floorplans[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003: 22(10).
[40]罗罹.基于门控时钟的CMOS电路低功耗设计[J].安徽大学学报,2005,29(3):21-24.
[41]徐如淏,李宇飞,胡嘉圣.基于时钟控制的低功耗电路设计[J].计算机工程,2005,31(4): 206-208.
[42] W.Liao, J.Basile, L.He. Leakage Power Modeling and Reduction with Data Retention [J]. In: Proc of ACMICCAD, SanJose, 2002, 714-719.
[43]段炼,许浒,王逵,程旭.给定偏差约束条件下的时钟布线局部拓扑构造优化算法[J].计算机辅助设计与图形学学报,2008,20(4): 452-458.
[44] CADENCE. Encounter user guide[K]. 2007.
[45] Oklobdzija V G, Stojanovic V M, Markovic D M, et al. Digital System Clocking: High-Performance and Low2Power Aspects[M]. Willey-Interscience, 2003.
[46] Su H, Sapatnekar S S. Hybrid Structured Clock Network Construction[A]. Proc of ICCAD’01[C]. 2001: 333-336.
[47] Friedman E G. Clock Dist ribution Networks in Synchronous Digital Integrated Circuits[J]. Proceedings of the IEEE, 2001, 89(5): 665-692.
[48] Rusu S, Tam S. Clock Generation and Distribution for the First IA-64 Microprocessor[J]. IEEE Journal of Solid State Circuit, 2000, 35(11): 1545-1552.
[49] Kurd N A, Barkatullah J S, Dizon R O. A Multigigahertz Clocking Scheme for the Pentium 4 Microprocessor[J]. IEEE Journal of Solid State Circuit, 2001, 36(11): 1647-1653.
[50] Restle P J, McNamara T G, et al. A Clock Distribution Network for Microprocessors[J]. IEEE Journal of Solid State Circuit, 2001, 36(5): 792-799.
[51] Floyd B A, Guo X, Caserta J. Wireless Interconnects for Clock Distribution [A]. Proc of TAU’02[C]. 2002.
[52] Chung D, Ryu C, Kim H. A Chip Package Hybrid DLL Loop and Clock Distribution Network for Low-Jitter Clock Delivery[A]. Proc of ISSCC’05[C]. 2005: 514-516.
[53] Mule’A V, Glyt sis E N, Gaylord T K, et al. Elect rical and Optical Clock Distribution Networks for Gigascale Microprocessors[J]. IEEE Trans on Very Large Scale Integration Systems, 2002, 10(5): 582-594.
[54] Ismail Y I, Friedman E G, Neves J. Exploiting the On-Chip Inductance in High-Speed Clock Distribution Networks[J]. IEEE Trans on Very Large Scale Integration Systems, 2001, 9(6): 963-973.
[55] Fossorier M P C. Quasicyclic Low-density Parity-check Codes from Circulant Pemutation Matrices[J]. IEEE Transactions on Information Theory, 2004, 50(8): 1788-1793.
[56] Hodges D A, Jackson H G,Saleh R A. Analysis and Design of Digital Intergreated Circuits: In Deep Submicron Technology [M]. 3rd Edition. McGraw Hill, 2003.
[57]胡峰.基于电力网数据传输芯片的时钟树综合技术研究[D].北京工业大学硕士学位论文,2009: 14-20.
[58] Oklobdzija V G, Stojanovic V M, Markovic D M, et al. Digital System Clocking: High-Performance and Low-Power Aspects[M]. Willey-Interscience, 2003.
[59] D. Wann, M. Franklin. A synchronous and clocked control structures for VLSI based interconnection networks [J]. IEEE Trans. Comput, 1983, 32: 284-293.
[60]汪珺.基于Garfield5设计中时钟树综合技术研究[D].东南大学硕士学位论文,2006: 1-30.
[61]赵萌,蔡懿慈,洪先龙.合理偏差驱动的时钟线网构造及优化[J].半导体学报,2003,24(4): 438-443.
[62]殷瑞相,郭瑢.同步数字集成电路设计中的时钟树分析[J].汕头大学学报.自然科学版,2005,20(3): 75-80.
[63] Chi M C, Huang S H. A reliable clock tree design methodology for ASIC designs[J ]. Chung Yuan Journal, 2000, 28 (3): 115-122.
[64] Chung J, Cheng C K. Optimal buffered clock tree synthesis[C]. ASIC Conference and Exhibit, Proceedings, Seventh Annual IEEE International , USA: Rochester, 1994: 130-133.
[65]刘辉华,刘振,李蜀霞,何春,饶全林.层次化时钟网络设计研究[J].微电子学与计算机,2008,25(11): 52-53.
[66] D.G.Chinnery, B.Nikolic,K.Keutzer. Achiving 550MHz in an ASIC Methodology[C]. Design Automation Conference, DAC, 2001: 420-425.
[67] M.Charikar, J.Kleinberg, R.Kumar, S.Rajagopalan, A.Sahai, A.Tomkins. Minimizing wirelength in zero and bounded skew clock trees[C]. Proc. ACM/SIAM Symp. DiscreteAlgorithms, Baltimore, 1999: 177-184.
[68]鲍进威,田丰,喻小虎,张建,欧钢.一种改进的时钟网络设计方法及实现[J].全球定位系统,2011,36(4): 51-55.
[69]顾琴,辜建伟,李玉童.在Encounter中实现网格+局部树的时钟设计流程[J].电子设计应用,2008,12: 57-58.
[70]王延升,刘雷波. SoC设计中的时钟低功耗技术[J].计算机工程,2009,35(24): 257-261.
[71] Chao T H, H su Y C, Ho J M. Zero skew clock net routing[C]. 29th ACM/IEEE Design Automation Conference, 1992: 518-520.
[72]李芝燕,严晓浪.高速多级时钟网布线[J].半导体学报,2000,21(3): 290-293.
[73] Kahng A B, Cong J, Robins G. High-performance clock routing based on recursive geometric matching[C]. Proc ACM/IEEEm Design Automation Conf, 1991: 322-324.
[74]常晓夏,潘亮,李勇.射频识别芯片设计中时钟树功耗的优化与实现[J].中国集成电路,2011: 36-40.
[75]韩彤辉.基于网表层次的多时钟域时序优化研究[D].上海大学硕士学位论文,2007: 16-20.
[76] Zhang B, Balasinski A, Ma T P. Hot-Carrier Effects on GIDL (Gate-Induced-Drain-Leakage) Current in Thin-Film SOI/NMOSFET and its Application in Measuring Lateral Bipolar Current Gain [J]. IEEE Electron Device Letters, 1994, 15(5): 165-175.
[2]催义智.低功耗技术在后端设计中的应用[D].复旦大学硕士学位论文,2008: 1-30.
[3] M.Keating, P.Bricaud. Reuse Methodology Manual for System-On-Chip Design. Boston/Dorecht/London: Kluwer[M]. Academic Publishers, 2000.
[4]唐杉,徐强,王莉薇.数字IC设计[M].机械工业出版社,2006 :59-62.
[5]魏敬和,吴晓洁,虞致. SoC低功耗设计及其技术实现[J].电子与封装,2009,9(5): 20-23.
[6]张富彬, HO Ching-Yen,彭思龙. SoC设计中的低功耗策略[J].电子器件,2007,30(4): 633-636.
[7]王延升,刘雷波. SoC设计中的时钟低功耗技术[J].计算机工程,2009,35(24): 257-261.
[8] Donno M, Macii E, Mazzoni L. Power-Aware Clock Tree Planning[A]. Proc of ISPD’04[C]. 2004: 138-147.
[9]赵丽莎,罗胜钦. SOC技术及系统级低功耗设计[J].电子与封装,2008,8(9): 27-32.
[10]郭小川.低功耗物理设计[D].复旦大学硕士学位论文,2007: 19-25.
[11]陈静华. SoC芯片低功耗设计[D].湖南大学硕士学位论文,2005: 1-25.
[12] Chandrakasan, S. Sheng, R. Brodersen.Low-Power CMOS Digital Design[J]. IEEE Jounral of Solid State Cireuits, 1992, 27(4): 473-484.
[13] Chandrakasnan, R. Brodersen. Minimizing Power ConsumPtionin Digital CMOS Circuits[J]. Proceedings of the IEEE, 1995, 83(4): 495-523.
[14] Kaushik Roy, Sharat Prasad. Low Power CMOS VLSI Cireuit Design[M]. NewYork: A Wiley Interseience Publication, 2000, 5-43.
[15] Siva Narendra, Vivek De, Shekhar Borkar, et al. Full-Chip Subthreshold Leakage Power Prediction and Reduetion Techniquesfor Sub 0.18um CMOS[J]. IEEE Journal of Solid-State Circuits, 2004, 39(3): 131-139.
[16] Dongwoo Lee,David Blaauw, Dennis Sylvester. Gate Oxide Leakage Current Analysis and Reduction of VLSI Circuits[J]. IEEE Tran. On VLSI System, 2004, 12(2): 155-166.
[17] K. Roy, S. Mukhopadhyay, H. Mahmoodl. Leakage current mechanisms and leakage reduction teehniques in deep-submicrometer CMOS circuits[J]. Proceedings of the IEEE, 2003, 91(2): 305-327.
[18]黄伟坚.全芯片时钟网络的综合与优化方法[D].上海交通大学硕士学位论文,2010: 1-20.
[19]刘祥远,陈书明.高性能VLSI设计中时钟分布网络的问题与解决方法[J].计算机工程与科学,2007,29(6): 89-92.
[20] Alice Wang, Anantha P. Chandrakasan, Staphen V. Kosonocky, Optimal and Threshold Scaling for Subthreshold CMOS Circuits[J]. IEEE Computer Society Annual Symposium on VLSI, 2002.
[21] Jan M.Rabacy.数字集成电路设计与透视[M].清华大学出版社,1992.
[22] J.Cong, L.he, C.K.Koh, P.H.Madden. Performance Optimization of VLSI Interconnection Layout[J]. Integration, the VLSI Jounaral, 1996: 5-95.
[23]周凤亭.基于PC+ASTRO的深亚微米布局布线流程研究[D].东南大学硕士学位论文,2005: 1-40.
[24]咸德勇.深亚微米SoC的逻辑综合与版图设计[D].国防科大硕士学位论文,2006: 10-40.
[25] Hsiao-Pin Su, Youn-Long Lin. A timing-driven Soft-macro Placement and Resynthesis Method in Interaction with Chip Floorplanning [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999, 18(4): 475-483.
[26] Roy K, Prasad S. Low Power CMOS VLSI Circuit Design [M]. New York: A Wiley Interscience Publication, 2000.
[27]曾璇,周丽丽,黄晟,周电,李威.时钟延时及偏差最小化的缓冲器插入新算法[J].电子学报,2001,29(11): 1458-1462.
[28] YEH C, WILKE G, CHEN H. Clock distribution architecture: a comparative study[C]. Proc of the Int Symp on Quality Electronic Design. San Jose, CA, USA , 2006: 85-91.
[29] WILKE G R, MURGAI R. Design and analysis of“Tree +Local Meshes”clock architecture[C]. Proc of the Int Symp on Quality Electronic Design. San Jose, CA, USA, 2007: 165-170.
[30]马光胜,冯刚. SoC设计与IP核重用技术[M].国防工业出版社,2006.
[31] Cadence. RTL Compiler Manul[K], Version 7.1. 2007.
[32]郭小川.低功耗物理设计[D].复旦大学硕士学位论文,2007: 19-25.
[33]王彬,任艳颖.数字IC系统设计[J].西安电子科技大学. 2005:207-214.
[34]王超.语音SoC芯片数字后端低功耗研究[D].哈尔滨工业大学硕士学位论文,2010: 1-50.
[35]张宇弘.行为逻辑层上的SoC低功耗设计[D].浙江大学博士学位论文,2004: 1-15.
[36]郭炜,郭筝,谢憬. SoC设计方法与实现[M].电子工业出版社,2007.
[37]陈春章,艾霞,王国雄.数字集成电路物理设计[M].科学出版社,2008.
[38] Patnekar S S. High-performance power grids for nanometer technologies[J]. Proceedings of 17th International Conference on VLSI Design. 2004: 839-844.
[39] Zion Cien Shen, Chris C. N. Chu. Bounds on the Number of Slicing, Mosaic, and Genernal Floorplans[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003: 22(10).
[40]罗罹.基于门控时钟的CMOS电路低功耗设计[J].安徽大学学报,2005,29(3):21-24.
[41]徐如淏,李宇飞,胡嘉圣.基于时钟控制的低功耗电路设计[J].计算机工程,2005,31(4): 206-208.
[42] W.Liao, J.Basile, L.He. Leakage Power Modeling and Reduction with Data Retention [J]. In: Proc of ACMICCAD, SanJose, 2002, 714-719.
[43]段炼,许浒,王逵,程旭.给定偏差约束条件下的时钟布线局部拓扑构造优化算法[J].计算机辅助设计与图形学学报,2008,20(4): 452-458.
[44] CADENCE. Encounter user guide[K]. 2007.
[45] Oklobdzija V G, Stojanovic V M, Markovic D M, et al. Digital System Clocking: High-Performance and Low2Power Aspects[M]. Willey-Interscience, 2003.
[46] Su H, Sapatnekar S S. Hybrid Structured Clock Network Construction[A]. Proc of ICCAD’01[C]. 2001: 333-336.
[47] Friedman E G. Clock Dist ribution Networks in Synchronous Digital Integrated Circuits[J]. Proceedings of the IEEE, 2001, 89(5): 665-692.
[48] Rusu S, Tam S. Clock Generation and Distribution for the First IA-64 Microprocessor[J]. IEEE Journal of Solid State Circuit, 2000, 35(11): 1545-1552.
[49] Kurd N A, Barkatullah J S, Dizon R O. A Multigigahertz Clocking Scheme for the Pentium 4 Microprocessor[J]. IEEE Journal of Solid State Circuit, 2001, 36(11): 1647-1653.
[50] Restle P J, McNamara T G, et al. A Clock Distribution Network for Microprocessors[J]. IEEE Journal of Solid State Circuit, 2001, 36(5): 792-799.
[51] Floyd B A, Guo X, Caserta J. Wireless Interconnects for Clock Distribution [A]. Proc of TAU’02[C]. 2002.
[52] Chung D, Ryu C, Kim H. A Chip Package Hybrid DLL Loop and Clock Distribution Network for Low-Jitter Clock Delivery[A]. Proc of ISSCC’05[C]. 2005: 514-516.
[53] Mule’A V, Glyt sis E N, Gaylord T K, et al. Elect rical and Optical Clock Distribution Networks for Gigascale Microprocessors[J]. IEEE Trans on Very Large Scale Integration Systems, 2002, 10(5): 582-594.
[54] Ismail Y I, Friedman E G, Neves J. Exploiting the On-Chip Inductance in High-Speed Clock Distribution Networks[J]. IEEE Trans on Very Large Scale Integration Systems, 2001, 9(6): 963-973.
[55] Fossorier M P C. Quasicyclic Low-density Parity-check Codes from Circulant Pemutation Matrices[J]. IEEE Transactions on Information Theory, 2004, 50(8): 1788-1793.
[56] Hodges D A, Jackson H G,Saleh R A. Analysis and Design of Digital Intergreated Circuits: In Deep Submicron Technology [M]. 3rd Edition. McGraw Hill, 2003.
[57]胡峰.基于电力网数据传输芯片的时钟树综合技术研究[D].北京工业大学硕士学位论文,2009: 14-20.
[58] Oklobdzija V G, Stojanovic V M, Markovic D M, et al. Digital System Clocking: High-Performance and Low-Power Aspects[M]. Willey-Interscience, 2003.
[59] D. Wann, M. Franklin. A synchronous and clocked control structures for VLSI based interconnection networks [J]. IEEE Trans. Comput, 1983, 32: 284-293.
[60]汪珺.基于Garfield5设计中时钟树综合技术研究[D].东南大学硕士学位论文,2006: 1-30.
[61]赵萌,蔡懿慈,洪先龙.合理偏差驱动的时钟线网构造及优化[J].半导体学报,2003,24(4): 438-443.
[62]殷瑞相,郭瑢.同步数字集成电路设计中的时钟树分析[J].汕头大学学报.自然科学版,2005,20(3): 75-80.
[63] Chi M C, Huang S H. A reliable clock tree design methodology for ASIC designs[J ]. Chung Yuan Journal, 2000, 28 (3): 115-122.
[64] Chung J, Cheng C K. Optimal buffered clock tree synthesis[C]. ASIC Conference and Exhibit, Proceedings, Seventh Annual IEEE International , USA: Rochester, 1994: 130-133.
[65]刘辉华,刘振,李蜀霞,何春,饶全林.层次化时钟网络设计研究[J].微电子学与计算机,2008,25(11): 52-53.
[66] D.G.Chinnery, B.Nikolic,K.Keutzer. Achiving 550MHz in an ASIC Methodology[C]. Design Automation Conference, DAC, 2001: 420-425.
[67] M.Charikar, J.Kleinberg, R.Kumar, S.Rajagopalan, A.Sahai, A.Tomkins. Minimizing wirelength in zero and bounded skew clock trees[C]. Proc. ACM/SIAM Symp. DiscreteAlgorithms, Baltimore, 1999: 177-184.
[68]鲍进威,田丰,喻小虎,张建,欧钢.一种改进的时钟网络设计方法及实现[J].全球定位系统,2011,36(4): 51-55.
[69]顾琴,辜建伟,李玉童.在Encounter中实现网格+局部树的时钟设计流程[J].电子设计应用,2008,12: 57-58.
[70]王延升,刘雷波. SoC设计中的时钟低功耗技术[J].计算机工程,2009,35(24): 257-261.
[71] Chao T H, H su Y C, Ho J M. Zero skew clock net routing[C]. 29th ACM/IEEE Design Automation Conference, 1992: 518-520.
[72]李芝燕,严晓浪.高速多级时钟网布线[J].半导体学报,2000,21(3): 290-293.
[73] Kahng A B, Cong J, Robins G. High-performance clock routing based on recursive geometric matching[C]. Proc ACM/IEEEm Design Automation Conf, 1991: 322-324.
[74]常晓夏,潘亮,李勇.射频识别芯片设计中时钟树功耗的优化与实现[J].中国集成电路,2011: 36-40.
[75]韩彤辉.基于网表层次的多时钟域时序优化研究[D].上海大学硕士学位论文,2007: 16-20.
[76] Zhang B, Balasinski A, Ma T P. Hot-Carrier Effects on GIDL (Gate-Induced-Drain-Leakage) Current in Thin-Film SOI/NMOSFET and its Application in Measuring Lateral Bipolar Current Gain [J]. IEEE Electron Device Letters, 1994, 15(5): 165-175.