嵌入式微处理器中动态可配置Cache结构的研究
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摘要
随着集成电路进入深亚微米和纳米级工艺阶段，嵌入式微处理器的功耗问题日益严重，功耗问题已经成为制约新一代微处理器发展最主要因素之一。在现代微处理器结构中，Cache作为微处理器和主存之间的桥梁，虽然极大地提高了系统性能，但它无论在芯片面积还是功耗上都占相当大的比重，Cache的功耗甚至对整个嵌入式系统的功耗具有决定性作用。因此，Cache的低功耗研究一直以来都是处理器体系结构领域的热点问题之一。
不同嵌入式程序对Cache结构的需求差别很大，即使同一应用程序，在不同时间片段对Cache的需求也不一样。传统Cache的结构一般固定不变，经常会出现与应用程序不匹配的现象。本文以提高Cache的能量效率出发，深入研究动态可配置的Cache结构，它在程序运行过程中，动态调整自身的结构，以满足程序的实时需求，在不影响性能的前提下，达到降低功耗的目的。本文的主要创新点与贡献如下：
首先，研究一种容量动态可配置的Cache结构，根据程序的实时需求，关闭处于空闲状态的存储资源，实现有效容量的调整。主要研究内容包括：分析一种容量可调整的Cache结构，通过使能信号控制各路的打开或关断，改变Cache的有效容量。研究一种高效的失效率硬件监测机制，通过添加辅助标志阵列，监测每种候选容量的失效率，并引入部分标志比较技术降低硬件开销。建立Cache体系结构级功耗模型，作为所有候选容量的评估标准。研究容量动态配置算法，在所有候选容量之中进行设计空间探索，为当前应用程序选择最匹配的Cache容量。
其次，研究一种相联度动态可配置的Cache结构，当发生程序相变时，触发仲裁机制对相联度重新配置，为当前程序选择最匹配的映射方式。主要研究内容包括：量化分析相联度对Cache性能和功耗的影响，并详细讨论路串联结构的工作原理。建立一种仲裁机制，监测程序访存特征行为，当发生程序相变时，在各种候选相联度之间进行设计空间探索。研究一种自适应的阈值策略，自动调节仲裁机制中阈值大小，提高仲裁机制的准确性和效率。
最后，将前面两种结构叠加，研究一种容量／相联度均动态可配置的Cache结构，在程序运行期间，能够同时动态调整Cache的有效容量和相联度，极大提高Cache的结构配置空间。主要研究内容包括：详细讨论Cache的组织结构和工作原理，并对硬件开销进行分析。建立一种高效的配置策略，由于同时对容量和相联度调整，使得候选Cache结构数目增大，高效的配置策略在庞大的设计空间中迅速找到最匹配的容量和相联度，极大地降低设计空间探索引起的时间和硬件开销。
As CMOS technology continues to scale down, microprocessors suffer more from the energy consumption problems. Nowadays, the energy consumption has become a major constraint in the state-of-art embedded microprocessors design. Caches are widely employed in modern microprocessor design to bridge the increasing speed gap between the processor and the off-chip main memory. Consequently, caches comsume a significant amount of the transistor budget and chip die area in microprocessors, and also the energy budget. Thus, the caches deserve a complete study of its energy behavior for the next generation microprocessors.
The demands for cache vary significantly from application to application and even within the different phases of a given application. Traditional cache has fixed architecture, which may not fit certain application. This thesis studies the dynamically reconfigurable cache architecture. The cache monitors and reacts to the phase changes in application, and dynamically adapts its architecture to meet the application's requirement. The evaluation results show that the dynamically reconfigurable cache can achieve a significant energy savings with minimal performance degradations. The following is the main contributions:
1. The On-line Cache Resizing (OCR) techniques are proposed. The OCR observes the application execution behavior, and dynamically enable/disable particular cache ways to make cache effective size changeable. First, a novel cache architecture which supports size change is analysed. Second, an execution monitoring mechanism employs additional tag array to observe the miss rate for each cache size. Finally, an architectural cache energy model is established. A reconfiguration algorithm is developed to evaluate each cache size and finally determine the optimal one.
2. The Reconfigurable-Associativity Cache (RAC) techniques are proposed. Whenever an application phase change is detected, the RAC triggers an associativity exploration behavior and sesearches the best one for current application. First, we analyse the associativity's impact on cache performance and energy consumption and discuss the way concatenation cache architecture. Second, an arbitration mechanism is developed to monitoring the application runtime behavior. Whenever there is a phase change, the mechanism explores each associativity candidate and determines the optimal one. Finally, an adaptive threshold strategy is studied, which makes the arbitration mechanism much more effective.
3. The Reconfigurable-Size/Associativity Cache (RSAC) techniques are proposed after combining the previous OCR and RAC. RSAC dynamically reconfigures both cache size and associativiy, which makes the reconfiguration space much larger. First, we describe the RSAC architecture and discuss the hardware implementation. Second, an efficient reconfiguration strategy is developed. Since the design space becomes larger, the efficiency of candidate cache exploration is important. A smart reconfiguration strategy can achieve a significant reduction in both hardware and energy overhead.
不同嵌入式程序对Cache结构的需求差别很大，即使同一应用程序，在不同时间片段对Cache的需求也不一样。传统Cache的结构一般固定不变，经常会出现与应用程序不匹配的现象。本文以提高Cache的能量效率出发，深入研究动态可配置的Cache结构，它在程序运行过程中，动态调整自身的结构，以满足程序的实时需求，在不影响性能的前提下，达到降低功耗的目的。本文的主要创新点与贡献如下：
首先，研究一种容量动态可配置的Cache结构，根据程序的实时需求，关闭处于空闲状态的存储资源，实现有效容量的调整。主要研究内容包括：分析一种容量可调整的Cache结构，通过使能信号控制各路的打开或关断，改变Cache的有效容量。研究一种高效的失效率硬件监测机制，通过添加辅助标志阵列，监测每种候选容量的失效率，并引入部分标志比较技术降低硬件开销。建立Cache体系结构级功耗模型，作为所有候选容量的评估标准。研究容量动态配置算法，在所有候选容量之中进行设计空间探索，为当前应用程序选择最匹配的Cache容量。
其次，研究一种相联度动态可配置的Cache结构，当发生程序相变时，触发仲裁机制对相联度重新配置，为当前程序选择最匹配的映射方式。主要研究内容包括：量化分析相联度对Cache性能和功耗的影响，并详细讨论路串联结构的工作原理。建立一种仲裁机制，监测程序访存特征行为，当发生程序相变时，在各种候选相联度之间进行设计空间探索。研究一种自适应的阈值策略，自动调节仲裁机制中阈值大小，提高仲裁机制的准确性和效率。
最后，将前面两种结构叠加，研究一种容量／相联度均动态可配置的Cache结构，在程序运行期间，能够同时动态调整Cache的有效容量和相联度，极大提高Cache的结构配置空间。主要研究内容包括：详细讨论Cache的组织结构和工作原理，并对硬件开销进行分析。建立一种高效的配置策略，由于同时对容量和相联度调整，使得候选Cache结构数目增大，高效的配置策略在庞大的设计空间中迅速找到最匹配的容量和相联度，极大地降低设计空间探索引起的时间和硬件开销。
As CMOS technology continues to scale down, microprocessors suffer more from the energy consumption problems. Nowadays, the energy consumption has become a major constraint in the state-of-art embedded microprocessors design. Caches are widely employed in modern microprocessor design to bridge the increasing speed gap between the processor and the off-chip main memory. Consequently, caches comsume a significant amount of the transistor budget and chip die area in microprocessors, and also the energy budget. Thus, the caches deserve a complete study of its energy behavior for the next generation microprocessors.
The demands for cache vary significantly from application to application and even within the different phases of a given application. Traditional cache has fixed architecture, which may not fit certain application. This thesis studies the dynamically reconfigurable cache architecture. The cache monitors and reacts to the phase changes in application, and dynamically adapts its architecture to meet the application's requirement. The evaluation results show that the dynamically reconfigurable cache can achieve a significant energy savings with minimal performance degradations. The following is the main contributions:
1. The On-line Cache Resizing (OCR) techniques are proposed. The OCR observes the application execution behavior, and dynamically enable/disable particular cache ways to make cache effective size changeable. First, a novel cache architecture which supports size change is analysed. Second, an execution monitoring mechanism employs additional tag array to observe the miss rate for each cache size. Finally, an architectural cache energy model is established. A reconfiguration algorithm is developed to evaluate each cache size and finally determine the optimal one.
2. The Reconfigurable-Associativity Cache (RAC) techniques are proposed. Whenever an application phase change is detected, the RAC triggers an associativity exploration behavior and sesearches the best one for current application. First, we analyse the associativity's impact on cache performance and energy consumption and discuss the way concatenation cache architecture. Second, an arbitration mechanism is developed to monitoring the application runtime behavior. Whenever there is a phase change, the mechanism explores each associativity candidate and determines the optimal one. Finally, an adaptive threshold strategy is studied, which makes the arbitration mechanism much more effective.
3. The Reconfigurable-Size/Associativity Cache (RSAC) techniques are proposed after combining the previous OCR and RAC. RSAC dynamically reconfigures both cache size and associativiy, which makes the reconfiguration space much larger. First, we describe the RSAC architecture and discuss the hardware implementation. Second, an efficient reconfiguration strategy is developed. Since the design space becomes larger, the efficiency of candidate cache exploration is important. A smart reconfiguration strategy can achieve a significant reduction in both hardware and energy overhead.
引文
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