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PXI/PCI总线设备驱动程序设计及应用
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摘要
PCI总线是一种高性能的系统局部总线,是个人电脑中使用最为广泛的接口,PXI(PCI eXtension for Instrumentation)总线是一种专门为工业数据采集和自动化应用量身定制的模块化仪器平台,是Compact PCI规范的拓展。除了机械、电气等因素之外,核心信号的定义基本相同。PCI总线的时钟频率为33MHz,总线32位,在理论情况下可以达到132MB/s的传输速度,在一般的图像数据采集、工业控制等应用中,性能突出。另外,地址线和数据线采用时分复用模式,大大地降低了接口的占用面积,同时各种桥接芯片、总线接口逻辑IP Core相对成熟,将PXI/PCI总线应用于嵌入式系统中,并不复杂。
     在Windows2000/XP平台下,开发PXI/PCI总线设备驱动程序,参照PCI总线规范,遵循微软的WDM(Windows Driver Model)驱动模型,进行内核编程,合理地获取PCI设备的配置空间、端口、存储器、DMA、中断等资源,在驱动程序中提供应用程序访问的接口,最终实现应用程序对设备的PCI访问,同底层硬件进行慢速、少量(单周期访问)或者快速、大量(DMA访问)的数据传输。
     在本文中,设备驱动程序分别应用于两个项目中,一个是基于PXI总线的实时图像采集与硬件调试系统,另一个是基于PXI/PCI总线的MIC通讯模块开发。在基于PXI总线的实时图像采集与硬件调试系统项目中,采用PCI9054作为桥接芯片,本地端连接到DSP芯片的主机接口,另一端直接同PXI总线相连接,通过驱动编程,提供给应用程序访问底层硬件的接口。在数据传输上,实现了对底层硬件数据的单周期读写访问和DMA传输。在此基础上,基于微软的MFC,编写上位机软件,实现了DSP程序加载、图像采集、算法选择、算法参数修改、联合调试等功能。
     在基于PXI/PCI总线的MIC通讯模块中,通过FPGA直接同PXI/PCI总线连接,接口逻辑采用IP Core的形式,配置成32位从模式,同时根据底层硬件资源的需要,合理设置IP Core的资源参数。在驱动编程中,同PCI9054的驱动相比,修改PCI设备资源获取部分代码,同时修改应用程序调用驱动的接口代码,编写测试软件,成功实现了对底层硬件资源的访问。在此基础上,编写电脑端控制软件,实现了对MIC通讯模块的模式配置、各种工作模式数据产生与保存、对各种模式的数据的访问,最终实现了各种模式的全部适用性命令/响应通讯测试。
PCI bus is a high-performance system local bus and the most widely used interface in personal computers, PXI bus is a modular instrument platform, which is tailored for industrial data acquisition and automation applications, and is the expansion of Compact PCI standard. Except for the factors such as mechanical, electrical, and so on, on the definition of core signals, PCI bus and PXI bus are basically the same. PCI bus’s clock frequency is 33MHz, and its width is 32-bit, which can achieve 132MB/s transmission speed in theory circumstances, in common applications such as image data acquisition and industrial control, it has outstanding performance. On the other hand, the address bus and data bus use time multiplex pattern which greatly reduces the interface occupying space, in addition, various bridging chips and bus interface logic IP core are relatively mature, which makes the applications of PXI/PCI in embedded systems not complicated.
     In Windows 2000/XP flat, we develop PXI/PCI bus device drivers, consulting PCI bus norms, following Microsoft WDM (Windows Driver Model), using kernel programming, and reasonable accessing PCI device configuration space, ports, memory, DMA, interruption resources, and so on, supplying applications access interfaces in driver, which finally realizes the application equipment with underlying hardware PCI access for slow, few (single cycle access) or quick, large (DMA) data transmission.
     In this paper, device drivers were applied to two projects, one is the Real-Time Video Signal Processing System Based on PXI Bus, and another is the MIC Communication Module Design Based on PXI/PCI Bus.
     In the Real-Time Video Signal Processing System Based on PXI Bus project, using PCI9054 as bridging chip whose local is connected to the host interface of DSP chip and the other kind is connected to PXI bus, through driver programming, it offers the interface for applications access to low-level hardware. Based on data transmission, realize the underlying hardware single cycle read/write access and DMA transmission. On this basis, based on Microsoft’MFC, compiling PC control software, realized the DSP program loading, image acquisition, algorithm select, algorithm parameter modification, joint commissioning etc. function.
     In the MIC Communication Module Design Based on PXI/PCI Bus project, through FPGA directly with PXI/PCI bus connections, interface using IP core logic which is configured to 32 bits form mode, and according to the need of underlying hardware resources, setting up reasonable IP core resources parameters. The driver programming, compared with PCI9054 driver, modify PCI device resources acquisition part code, and revised applications call driver’s interface, write testing software, successfully implementation of underlying hardware resources access. On this basis, programming the PC control software, realize the MIC communication module mode setting, all kinds of work mode data creation and preservation, data access of various modes, and finally achieve the various modes of all applicability command/response communication measurement.
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