宽带接收机前端射频电路设计
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摘要
无线通信和导航技术的迅速发展对宽带接收机前端射频电路提出了越来越高的要求，混频器是接收机的核心模块，其性能直接影响整个系统的性能及系统对其他模块的功能要求。基于可重构技术的混频器设计尤为重要。
本文中通信可配置频率主要在RFID、TD-SCDMA、WCDMA、GSM18OO的应用中，导航可配置频率分别应用到GPS和北斗卫星。论文首先给出了可重构系统的研究背景，介绍可重构技术四个方面的主要应用，同时对可重构器件也作了简要说明。
其次，本文对射频无线接收机中混频器模块进行了详细的研究，从混频器概念、工作原理和性能指标几个方面进行逐一介绍。接着给出了有源和无源混频器的结构，分析各种混频器的优缺点，确定本文的可重构混频器电路中核心部分电路采用Gilbert双平衡混频器实现。然后，在此基础上对电路进行改进，采用交流藕合互补跨导级，有效提高了混频器的各项性能。可重构电路设计部分，主要应用软件控制，实现硬件结构的可重构。可重构结构的具体方法是采用Verilog语言描述的MOS开关选通LC选频网络。
基于SMIC 0.18μm RF CMOS工艺，使用Cadenee软件的Spectre RF仿真工具，对设计的电路进行功能验证。仿真结果表明，载波频率为920MHZ时，可重构混频器的电压转换增益达到22.32dB;ldB压缩点为-18.78dB;电源电压1.8V时，电路功耗为0.967mW。最后，采用Virtuoso Layout Editor工具完成版图设计，通过DRC、LVS检查，完成参数提取，验证了版图设计的正确性。本文所设计的混频器具有较好的性能，在通信可配置中的五个频段和导航可配置的两个频段均实现混频，符合宽带接收机前端射频电路对可重构混频器模块的要求。
论文中共有图34幅，表3个，参考文献33篇。
The rapid development of wireless communication and navigation technology requires higher performance for broadband receiver front-end RF circuit. The mixer is an important block in receivers, and its performance has a direct influence upon that of the whole system and upon the demands of the system for other blocks. Design the mixer based on reconfigurable technology is especially important.
In this paper, the communication systems can be configured frequency basically used in RFID, TD-SCDMA, WCDMA, GSM1800 applications, navigation configurable frequency are applied to the GPS and Compass satellites. Firstly, this paper defined the background about the reconfigurable system and introduced the reconfigurable technology from four aspects of the main application. It also made a brief explanation for reconfigurable devices.
Secondly, detailed study of the mixers module of RF wireless receivers was discussed in paper, the concept and architecture of the mixer were explored. The working principles and performance specifications of the mixer were introduced, then the active and passive mixers structure were investigated. The advantages and drawbacks of various mixers was analyzed, the core of the mixer is a Gilbert double balanced mixer unit. Then, applying a coupling complementary transconductance, on the basis of the mixers modification design, to improve various performance of the mixer. Regarding the reconfigurable circuit design, the control of software was employed to achieve the hardware structure reconfigurable. The concrete method is to use MOS switch, which is described by Verilog language, to choose LC frequency selective network.
By using the standard SMIC 0.18um CMOS technology process parameters, the simulating was performed for the circuit with the SpectreRF of Cadence. When the carrier frequency is 920MHz, the simulation results revealed that the voltage conversion gain could achieve 22.32dB. 1dB compression point was about -18.78dBm. The total Power dissipation was about 0.967mW when the supply was 1.8V.
Finally, Employing Virtuoso Layout Editor to accomplish the layout design, and the DRC、LVS verification were successfully carried out. The approved mixer has good performance, which meets the reconfigurable mixers module requirements in broadband receiver front-end RF circuit.
This paper has 34 pictures,3 tables,33 references.
本文中通信可配置频率主要在RFID、TD-SCDMA、WCDMA、GSM18OO的应用中，导航可配置频率分别应用到GPS和北斗卫星。论文首先给出了可重构系统的研究背景，介绍可重构技术四个方面的主要应用，同时对可重构器件也作了简要说明。
其次，本文对射频无线接收机中混频器模块进行了详细的研究，从混频器概念、工作原理和性能指标几个方面进行逐一介绍。接着给出了有源和无源混频器的结构，分析各种混频器的优缺点，确定本文的可重构混频器电路中核心部分电路采用Gilbert双平衡混频器实现。然后，在此基础上对电路进行改进，采用交流藕合互补跨导级，有效提高了混频器的各项性能。可重构电路设计部分，主要应用软件控制，实现硬件结构的可重构。可重构结构的具体方法是采用Verilog语言描述的MOS开关选通LC选频网络。
基于SMIC 0.18μm RF CMOS工艺，使用Cadenee软件的Spectre RF仿真工具，对设计的电路进行功能验证。仿真结果表明，载波频率为920MHZ时，可重构混频器的电压转换增益达到22.32dB;ldB压缩点为-18.78dB;电源电压1.8V时，电路功耗为0.967mW。最后，采用Virtuoso Layout Editor工具完成版图设计，通过DRC、LVS检查，完成参数提取，验证了版图设计的正确性。本文所设计的混频器具有较好的性能，在通信可配置中的五个频段和导航可配置的两个频段均实现混频，符合宽带接收机前端射频电路对可重构混频器模块的要求。
论文中共有图34幅，表3个，参考文献33篇。
The rapid development of wireless communication and navigation technology requires higher performance for broadband receiver front-end RF circuit. The mixer is an important block in receivers, and its performance has a direct influence upon that of the whole system and upon the demands of the system for other blocks. Design the mixer based on reconfigurable technology is especially important.
In this paper, the communication systems can be configured frequency basically used in RFID, TD-SCDMA, WCDMA, GSM1800 applications, navigation configurable frequency are applied to the GPS and Compass satellites. Firstly, this paper defined the background about the reconfigurable system and introduced the reconfigurable technology from four aspects of the main application. It also made a brief explanation for reconfigurable devices.
Secondly, detailed study of the mixers module of RF wireless receivers was discussed in paper, the concept and architecture of the mixer were explored. The working principles and performance specifications of the mixer were introduced, then the active and passive mixers structure were investigated. The advantages and drawbacks of various mixers was analyzed, the core of the mixer is a Gilbert double balanced mixer unit. Then, applying a coupling complementary transconductance, on the basis of the mixers modification design, to improve various performance of the mixer. Regarding the reconfigurable circuit design, the control of software was employed to achieve the hardware structure reconfigurable. The concrete method is to use MOS switch, which is described by Verilog language, to choose LC frequency selective network.
By using the standard SMIC 0.18um CMOS technology process parameters, the simulating was performed for the circuit with the SpectreRF of Cadence. When the carrier frequency is 920MHz, the simulation results revealed that the voltage conversion gain could achieve 22.32dB. 1dB compression point was about -18.78dBm. The total Power dissipation was about 0.967mW when the supply was 1.8V.
Finally, Employing Virtuoso Layout Editor to accomplish the layout design, and the DRC、LVS verification were successfully carried out. The approved mixer has good performance, which meets the reconfigurable mixers module requirements in broadband receiver front-end RF circuit.
This paper has 34 pictures,3 tables,33 references.
引文
[1]王彬.未来无线通信发展趋势[J].发展,2008,4：91-91.
[2]黄开枝,王京等WCDMA无线通信系统的空时处理技术[J].电信技术,2001,9：30-32.
[3]李曼莉,张惠芳等,GPS系统及其应用新发展[J].河南测绘,2009,1：12-15.
[4]陈全育,夏光等.“北斗时代”离我们越来越近——来自第一届中国卫星导航学术年会的声音与成果[J].太空探索,2010,7：26-29.
[5]G Estrin, et al. Parallel Processing in a Restructurable Computer System[J]. Electronic Computers, IEEE Trans.1963, (12):747-755.
[6]Svetlana P. Kartashev, Steven I. Kartashev:Adaptive Assignment of Hardware Resources for Dynamic Architectures[C].IEEE Real-Time Systems Symposium.1981:130-143.
[7]Steven I. Kartashev, Svetlana P. Kartashev:A Multicomputer System with Dynamic Architecture[J]. Computers, IEEE Trans.1979,28(10):704-721.
[8]黄海鹰,黄华.动态重构逻辑及现状[J].微处理机,1998,4：1-3.
[9]朱明程FPGA动态可重构数字电路容错系统的研究[J].东南大学学报,2000,30(4)：138-142.
[10]鲍晓宇,施克仁.可重构信息处理[J].计算机自动测量与控制2000,1(8)：1-4.
[11]安军社,李杨等.一种高性能、高可靠、可重构计算机的设计与实现[J].计算机工程,2004,19(30)：139-143.
[12]梁甲华,林争辉等.基于可重构FPGA技术的自适应FIR滤波器的实现[J].电子工程师,2004,12(30)：48-50.
[13]武文权.可重构并行小卫星星载计算机体系结构设计[D].上海：中国科学院上海微系统与信息技术研究所,2004.
[14]杜文志.航天器FPGA在系统局部重构容错设计研究[J].中国空间技术科学2005,5：10-16.
[15]陆文斌,王成华.在系统可编程模拟器件的实时动态重构及应用[J].数字采集与处理2006,21(2)：245-250.
[16]R. Zebulum, A. Stoica, D. Keymeulen. A Flexible Model of a CMOS Field Programmable Transistor Array Targeted for Hardware Evolution[C].Third Int. Conference on Evolvable Systems: From Biology to Hardware (ICES2000),2000,4:274-283.
[17]Adrian Stoica, Ricardo Zebulum, Didier Keymeulen. Process and Challenges in Building Evolvable Devices[C].Third NASA/DOD Workshop on Evolvable Hardware,2001,7:33-35.
[18]A. Stoica, D. Keymeulen, et al. Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits[C]. Proceedings of the First NASA/DOD Workshop Evolvable Hardware,1999:76-84.
[19]A. Stoica, D. Keymeulen, R.S. Zebulum, et al. Evolvable, Reconfigurable Hardware for Future Space Systems[C].World Space Congress, International Astronautical Federation,2002.
[20]Natalie Clark, Paul Furth, Steven Horan. Intelligent Reconfigurable Integrated Satellite Processor[C].14th USU Conference on Small Satellites,2000:SSC00-VI-1.
[21]Christian F. da Silva, Alice M. Tokarnia. RECASTER:Synthesis of Fault-Tolerant Embedded Systems based on Dynamically Reconfigurable FPGAs[C]. Tokarnia Proceedings of the 18th International Parallel and Distributed Processing Symposium,2004,6:146.
[22]Manuel G Gericota, Gustavo R. Alves, et al. DRAFT An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs[C].Proceedings of the 7th International On-Line Testing Workshop, IEEE,2001:34-36.
[23]Anna Antola, Vincenzo Piuri, et al. On-line Diagnosis and Reconfiguration of FPGA Systems[C].Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications(DELTA2002),2002:291-296.
[24]Steve Casselman, John Schewel.Net Aware BitStreams that Upgrade FPGA Hardware Remotely over the Internet[C].Proceedings of SPIE,2002(4867).
[25]Haoyu Song, John W. Lockwood. Efficient Packet Classification for Network Intrusion Detection Using FPGA[C].Proceedings International Symposium on Field Programmable Gate Arrays (FPGA),2005:238-245.
[26]Daijin Kim, An Implementation of Fuzzy Logic Controller on the Reconfigurable FPGA System[J].IEEE Transactions on Industral Electronics,2000,47(3):703-715.
[27]Brian Schoner, Chris Jones, John Villasenor. Issues in Wireless Video Coding using Run-Time-Reconfigurable FPGAs[C]. Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines,1995:85-89.
[28]Jon Arnold, Adrian Caldow, Kevin Harman. A Reconfigurable 100 Mchip/s Spread Spectrum Receiver[C].Proceedings of IEEE International Conference on Acoustics, Speech, and Signal (ICASSP).2003(2):445-448.
[29]Tai Sasaki, Hiroshi Hataoka. Generation of Inter-or Cross-Modulation Distortions in Nonlinear Devices[C]. Cable Television, IEEE,2007: 131-137.
[30]任怀龙,默立冬,吴思汉等5.8GHzCMOS混频器设计[J].集成电路设计与开发,2008,33(3)：257-260.
[31]Mitrea O, Popa C, Manolescu A.M, et al. A Linearization Technique for Radio Frequency CMOS Gilbert-type Mixers[J]. IEEE.2003:1086-1089.
[32]Jianhui Wu, Zuotian Chen, Cheng Huang, et al. A3-band CMOS DTV Tuner IC for DVB-C Receiver. IEEE Transactions on Consumer Electronics[J],2007,53(4):1560-1568.
[33]Hooman Darabi, Senior Member, et al. A Noise Cancellation Technique in Active RF-CMOS Mixers[J]. IEEE Journal of Solid-State Circuits,2005,40(12):2628-2632.
[34]王良坤,马成炎,叶甜春.低噪声和高增益CMOS下变频混频器设计[J].微电子学,2008,38(5)：674-678.
[35]Vojkan Vidojkovic, Johan van der Tang, Arjan Leeuwenburgh et al. A Low-Voltage Folded-Switching Mixer in 0.18μm CMOS. IEEE Journal of Solid-State Circuits,2005,40(6): 1259-1264.
[36]刘高辉,余宁梅,董怀玉.用于超宽带无线通信系统的CMOS射频混频器的设计[J].电子器件,2005,28(4)：747-750.
[2]黄开枝,王京等WCDMA无线通信系统的空时处理技术[J].电信技术,2001,9：30-32.
[3]李曼莉,张惠芳等,GPS系统及其应用新发展[J].河南测绘,2009,1：12-15.
[4]陈全育,夏光等.“北斗时代”离我们越来越近——来自第一届中国卫星导航学术年会的声音与成果[J].太空探索,2010,7：26-29.
[5]G Estrin, et al. Parallel Processing in a Restructurable Computer System[J]. Electronic Computers, IEEE Trans.1963, (12):747-755.
[6]Svetlana P. Kartashev, Steven I. Kartashev:Adaptive Assignment of Hardware Resources for Dynamic Architectures[C].IEEE Real-Time Systems Symposium.1981:130-143.
[7]Steven I. Kartashev, Svetlana P. Kartashev:A Multicomputer System with Dynamic Architecture[J]. Computers, IEEE Trans.1979,28(10):704-721.
[8]黄海鹰,黄华.动态重构逻辑及现状[J].微处理机,1998,4：1-3.
[9]朱明程FPGA动态可重构数字电路容错系统的研究[J].东南大学学报,2000,30(4)：138-142.
[10]鲍晓宇,施克仁.可重构信息处理[J].计算机自动测量与控制2000,1(8)：1-4.
[11]安军社,李杨等.一种高性能、高可靠、可重构计算机的设计与实现[J].计算机工程,2004,19(30)：139-143.
[12]梁甲华,林争辉等.基于可重构FPGA技术的自适应FIR滤波器的实现[J].电子工程师,2004,12(30)：48-50.
[13]武文权.可重构并行小卫星星载计算机体系结构设计[D].上海：中国科学院上海微系统与信息技术研究所,2004.
[14]杜文志.航天器FPGA在系统局部重构容错设计研究[J].中国空间技术科学2005,5：10-16.
[15]陆文斌,王成华.在系统可编程模拟器件的实时动态重构及应用[J].数字采集与处理2006,21(2)：245-250.
[16]R. Zebulum, A. Stoica, D. Keymeulen. A Flexible Model of a CMOS Field Programmable Transistor Array Targeted for Hardware Evolution[C].Third Int. Conference on Evolvable Systems: From Biology to Hardware (ICES2000),2000,4:274-283.
[17]Adrian Stoica, Ricardo Zebulum, Didier Keymeulen. Process and Challenges in Building Evolvable Devices[C].Third NASA/DOD Workshop on Evolvable Hardware,2001,7:33-35.
[18]A. Stoica, D. Keymeulen, et al. Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits[C]. Proceedings of the First NASA/DOD Workshop Evolvable Hardware,1999:76-84.
[19]A. Stoica, D. Keymeulen, R.S. Zebulum, et al. Evolvable, Reconfigurable Hardware for Future Space Systems[C].World Space Congress, International Astronautical Federation,2002.
[20]Natalie Clark, Paul Furth, Steven Horan. Intelligent Reconfigurable Integrated Satellite Processor[C].14th USU Conference on Small Satellites,2000:SSC00-VI-1.
[21]Christian F. da Silva, Alice M. Tokarnia. RECASTER:Synthesis of Fault-Tolerant Embedded Systems based on Dynamically Reconfigurable FPGAs[C]. Tokarnia Proceedings of the 18th International Parallel and Distributed Processing Symposium,2004,6:146.
[22]Manuel G Gericota, Gustavo R. Alves, et al. DRAFT An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs[C].Proceedings of the 7th International On-Line Testing Workshop, IEEE,2001:34-36.
[23]Anna Antola, Vincenzo Piuri, et al. On-line Diagnosis and Reconfiguration of FPGA Systems[C].Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications(DELTA2002),2002:291-296.
[24]Steve Casselman, John Schewel.Net Aware BitStreams that Upgrade FPGA Hardware Remotely over the Internet[C].Proceedings of SPIE,2002(4867).
[25]Haoyu Song, John W. Lockwood. Efficient Packet Classification for Network Intrusion Detection Using FPGA[C].Proceedings International Symposium on Field Programmable Gate Arrays (FPGA),2005:238-245.
[26]Daijin Kim, An Implementation of Fuzzy Logic Controller on the Reconfigurable FPGA System[J].IEEE Transactions on Industral Electronics,2000,47(3):703-715.
[27]Brian Schoner, Chris Jones, John Villasenor. Issues in Wireless Video Coding using Run-Time-Reconfigurable FPGAs[C]. Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines,1995:85-89.
[28]Jon Arnold, Adrian Caldow, Kevin Harman. A Reconfigurable 100 Mchip/s Spread Spectrum Receiver[C].Proceedings of IEEE International Conference on Acoustics, Speech, and Signal (ICASSP).2003(2):445-448.
[29]Tai Sasaki, Hiroshi Hataoka. Generation of Inter-or Cross-Modulation Distortions in Nonlinear Devices[C]. Cable Television, IEEE,2007: 131-137.
[30]任怀龙,默立冬,吴思汉等5.8GHzCMOS混频器设计[J].集成电路设计与开发,2008,33(3)：257-260.
[31]Mitrea O, Popa C, Manolescu A.M, et al. A Linearization Technique for Radio Frequency CMOS Gilbert-type Mixers[J]. IEEE.2003:1086-1089.
[32]Jianhui Wu, Zuotian Chen, Cheng Huang, et al. A3-band CMOS DTV Tuner IC for DVB-C Receiver. IEEE Transactions on Consumer Electronics[J],2007,53(4):1560-1568.
[33]Hooman Darabi, Senior Member, et al. A Noise Cancellation Technique in Active RF-CMOS Mixers[J]. IEEE Journal of Solid-State Circuits,2005,40(12):2628-2632.
[34]王良坤,马成炎,叶甜春.低噪声和高增益CMOS下变频混频器设计[J].微电子学,2008,38(5)：674-678.
[35]Vojkan Vidojkovic, Johan van der Tang, Arjan Leeuwenburgh et al. A Low-Voltage Folded-Switching Mixer in 0.18μm CMOS. IEEE Journal of Solid-State Circuits,2005,40(6): 1259-1264.
[36]刘高辉,余宁梅,董怀玉.用于超宽带无线通信系统的CMOS射频混频器的设计[J].电子器件,2005,28(4)：747-750.