中频数字收发信机的研究与系统实现
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摘要
目前,随着技术的高速发展,越来越多的无线电收发信机功能适合采用数字技术设计和实现。因为数字技术相比较模拟技术具有很大的优越性,主要表现在处理精度高,灵活性好,设备体积小,功耗低,抗干扰能力强等方面。理想软件无线电要求A/D和D/A尽量向射频靠拢,而将尽可能多的无线电功能用软件加以实现。目前,受芯片制造技术的制约,软件无线电收发信机的功能还适合在中频上加以实现。研究的重点一方面是针对多种体制信号进行全数字化调制解调高效结构以及实现算法的研究,另一个方面就是采用高速A/D、D/A转换器以及高性能,大规模可编程器件进行样机的工程研制。这些工作对于将来实现理想软件无线电的功能无疑具有重要的理论和实践意义。
本文是围绕着中频数字收发信机的设计这一主题展开的。首先是关于2Mbps码率PCM/FM遥测数字接收机设计问题,主要包括三个研究点:1)提出了一种高效的数字FM解调算法;2)研究了PCM/FM信号的同步技术,包括载波同步和PCM码同步两方面,提出了一种载波频偏抑制的新方法;3)采用高速ADC,专用数字下变频器件(DDC)和FPGA设计和实现了PCM/FM中频数字化接收机,对其性能进行了实验测试。针对经典DDC方法难以实现宽带信号的有效接收问题,本文的第二个研究内容是关于四种高效的宽带数字下变频实现结构,能够解决其技术瓶颈。高速数传收发信机的设计是跟踪与数据中继卫星系统(TDRSS)的关键技术之一。本文的第三个研究内容关于800Mbps速率8PSK高速数传接收机的设计难题,主要研究点包括:1)提出了8PSK高速数传接收机的实现方案和频域并行处理解调算法,进行计算机仿真验证;2)采用超高速ADC和高性能FPGA设计和实现了8PSK高速数传接收机,对样机进行了测试。本文的第四个研究内容关于中频数字调制器设计和宽带频率合成技术,主要研究点包括三个方面:1)基于ICS564 DAC卡实现了4通道多模式中频数字调制器;2)提出了800Mbps速率8PSK高速数传中频调制器的实现方案,采用高性能FPGA和超高速DAC设计和实现了样机,给出了实验结果;3)采用一种改进的DDS+PLL的频率合成技术设计和实现了一种能够同时覆盖S、L和C波段的宽带低相噪频率合成器。
本文的主要创新之处:
(1)在PCM/FM中频数字化接收机的研究中,提出了一种高效的FM解调算法,它采用CORDIC(Coordinate Rotation Digital Computer)算法进行鉴相,再对鉴相结果进行一阶差分鉴频。该算法适合于在FPGA中以多级流水线结构实现,具有运算量小,处理速度快的优点;
(2)对PCM/FM中频数字化接收机的同步技术进行了研究,包括载波和码同步两方面。提出了一种基于滑窗幅度检波和抵消的载波频偏抑制新方法。该算法具有运算量小,对频偏变化适应能力强的优点;
(3)采用中频采样ADC,专用DDC器件和FPGA实现了PCM/FM中频数字化接收机,实验结果表明样机达到了较好的技术指标;
(4)研究了四种高效的宽带DDC实现结构:混频器后置结构、最小公倍数结构、一次变频结构和二次变频结构,能够有效地降低滤波和混频的乘法速度。
(5)针对800Mbps速率8PSK高速数传接收机的设计难题,提出了其实现方案以及频域并行处理的信号解调算法,计算机仿真结果证明了其可行性;
(6)采用超高速ADC和高性能FPGA完成8PSK高速数传接收机设计,实验结果表明样机能够正确地解调8PSK信号;
(7)提出了800Mbps速率8PSK高速数传中频调制器的实现方案,采用高性能FPGA和超高速DAC完成了样机设计,实验结果表明8PSK输出信号达到了较好的EVM(Error Vector Magnitude)指标;
(8)采用一种改进的DDS+PLL的频率合成技术,成功地设计出一种能够同时覆盖L、S、C频段的宽带低相噪频率合成器,达到了较好的技术指标。
At present, with the developments of techniques, more and more transceivers are fitted to be implemented with digital techniques. Because digital techniques are superior to their analog counterparts in aspects of higher accuracy, higher agility, smaller volume , lower power dissipation as well as better anti-jamming capacity. The ideal SDR requires ADC and DAC as close to the RF front end as possible, and realize as much as possible radio functions with software. Nowadays, SDR transceivers are suited to be realized at intermediate frequency due to the restrictions of chip manufacturing techniques. Researches are focus on all digital modulation demodulation structures and algorithms on the one hand and, and on the another hand on developing prototype with high speed A/D, D/A converters and high performance, large scale programmable chips. These efforts are of great importance to realize ideal SDR in the sense of theories and practices.
This thesis discusses some topics of designing IF digital transceivers. The first topic is about all digital PCM/FM telemetry receiver whose data rate is 2Mbps. Three items are included: 1) A new effective digital FM demodulation algorithm has been presented; 2) Carrier and PCM code synchronization techniques have been explored and a new carrier deviation suppression algorithm has been proposed; 3) A prototype of PCM/FM digital receiver which is designed and implemented with high speed ADC, dedicated DDC and FPGA has been tested in the lab. Because typical DDC method is hard to receive wideband signals, the second topic of the thesis is about effective wideband DDC implementation structures. Four structures have been studied, which can overcome difficulties of typical DDC method effectively. Design of all digital high data rate transmission transceivers is the key techniques of the TDRSS systems. The third topic of the thesis is concerned with the problem designing 800Mbps 8PSK receiver, two main items are included: 1) Implementation scheme and 8PSK demodulation algorithms have been proposed, which are performed in the frequency domain in parallel and verified by computer simulations; 2) A prototype of 8PSK receiver which is designed and implemented with super high speed A/D converter and high performance FPGA has been tested in the lab. The fourth topic of the thesis is about digital IF modulation and frequency synthesis techniques, three items are involved: 1) A four channel multimode digital IF modulator has been implemented based on the ICS-564A DAC card; 2) Implementation scheme of 800Mbps 8PSK wideband digital modulator has been put forward. A prototype which is designed with high performance FPGA and super high speed D/A converter has been tested in the lab; 3) A wideband low phase noise frequency synthesizer has been implemented with an improved DDS+PLL hybrid synthesis techniques, which can cover the S,L and C bands at one time.
The main creative points in this thesis are as follows:
1) In the research of the PCM/FM IF digital receiver, a high effective FM demodulation algorithm has been presented, which performs phase discrimination with CORDIC algorithm and then first order differential frequency discrimination to the phase discriminated results and is suited to be realized with FPGA in the form of multi-stage streamlined structure.
2) Carrier and timing synchronization techniques of the PCM/FM IF digital receiver have been studied. A new carrier deviation suppression algorithm has been proposed that can perform envelope detection with a slip window and then subtract detected results from the received signals, which consumes little amount of calculations and is adaptive to carrier variation.
3) A PCM/FM IF digital receiver has been implemented with IF sampling ADC, dedicated DDC and FPGA, which has better performances and is verified by experimental results.
4) Four effective wideband DDC implementation structure have been researched: mixer postpositional structure, the minimum common multiples structure, once frequency transfer structure and double frequency transfer structure, which can decrease multiplication speed of filtering and mixing in effect.
5) Implementation scheme and demodulation algorithms of 800Mbps 8PSK receiver have been presented which are performed in the frequency domain in parallel and verified by computer simulations.
6) An 800Mbps 8PSK receiver has been implemented with super high speed A/D converter and high performance FPGA, which can demodulate 8PSK signals correctly.
7) Design scheme of 800Mbps 8PSK IF modulator has been presented. A prototype has been implemented with high performance FPGA and super high speed D/A converter, which has better EVM performances verified by the experimental results.
8) A wideband low phase noise frequency synthesizer has been implemented with an improved DDS+PLL hybrid frequency synthesize technique which has better performances and can cover the L, S, C bands at one time.
本文是围绕着中频数字收发信机的设计这一主题展开的。首先是关于2Mbps码率PCM/FM遥测数字接收机设计问题,主要包括三个研究点:1)提出了一种高效的数字FM解调算法;2)研究了PCM/FM信号的同步技术,包括载波同步和PCM码同步两方面,提出了一种载波频偏抑制的新方法;3)采用高速ADC,专用数字下变频器件(DDC)和FPGA设计和实现了PCM/FM中频数字化接收机,对其性能进行了实验测试。针对经典DDC方法难以实现宽带信号的有效接收问题,本文的第二个研究内容是关于四种高效的宽带数字下变频实现结构,能够解决其技术瓶颈。高速数传收发信机的设计是跟踪与数据中继卫星系统(TDRSS)的关键技术之一。本文的第三个研究内容关于800Mbps速率8PSK高速数传接收机的设计难题,主要研究点包括:1)提出了8PSK高速数传接收机的实现方案和频域并行处理解调算法,进行计算机仿真验证;2)采用超高速ADC和高性能FPGA设计和实现了8PSK高速数传接收机,对样机进行了测试。本文的第四个研究内容关于中频数字调制器设计和宽带频率合成技术,主要研究点包括三个方面:1)基于ICS564 DAC卡实现了4通道多模式中频数字调制器;2)提出了800Mbps速率8PSK高速数传中频调制器的实现方案,采用高性能FPGA和超高速DAC设计和实现了样机,给出了实验结果;3)采用一种改进的DDS+PLL的频率合成技术设计和实现了一种能够同时覆盖S、L和C波段的宽带低相噪频率合成器。
本文的主要创新之处:
(1)在PCM/FM中频数字化接收机的研究中,提出了一种高效的FM解调算法,它采用CORDIC(Coordinate Rotation Digital Computer)算法进行鉴相,再对鉴相结果进行一阶差分鉴频。该算法适合于在FPGA中以多级流水线结构实现,具有运算量小,处理速度快的优点;
(2)对PCM/FM中频数字化接收机的同步技术进行了研究,包括载波和码同步两方面。提出了一种基于滑窗幅度检波和抵消的载波频偏抑制新方法。该算法具有运算量小,对频偏变化适应能力强的优点;
(3)采用中频采样ADC,专用DDC器件和FPGA实现了PCM/FM中频数字化接收机,实验结果表明样机达到了较好的技术指标;
(4)研究了四种高效的宽带DDC实现结构:混频器后置结构、最小公倍数结构、一次变频结构和二次变频结构,能够有效地降低滤波和混频的乘法速度。
(5)针对800Mbps速率8PSK高速数传接收机的设计难题,提出了其实现方案以及频域并行处理的信号解调算法,计算机仿真结果证明了其可行性;
(6)采用超高速ADC和高性能FPGA完成8PSK高速数传接收机设计,实验结果表明样机能够正确地解调8PSK信号;
(7)提出了800Mbps速率8PSK高速数传中频调制器的实现方案,采用高性能FPGA和超高速DAC完成了样机设计,实验结果表明8PSK输出信号达到了较好的EVM(Error Vector Magnitude)指标;
(8)采用一种改进的DDS+PLL的频率合成技术,成功地设计出一种能够同时覆盖L、S、C频段的宽带低相噪频率合成器,达到了较好的技术指标。
At present, with the developments of techniques, more and more transceivers are fitted to be implemented with digital techniques. Because digital techniques are superior to their analog counterparts in aspects of higher accuracy, higher agility, smaller volume , lower power dissipation as well as better anti-jamming capacity. The ideal SDR requires ADC and DAC as close to the RF front end as possible, and realize as much as possible radio functions with software. Nowadays, SDR transceivers are suited to be realized at intermediate frequency due to the restrictions of chip manufacturing techniques. Researches are focus on all digital modulation demodulation structures and algorithms on the one hand and, and on the another hand on developing prototype with high speed A/D, D/A converters and high performance, large scale programmable chips. These efforts are of great importance to realize ideal SDR in the sense of theories and practices.
This thesis discusses some topics of designing IF digital transceivers. The first topic is about all digital PCM/FM telemetry receiver whose data rate is 2Mbps. Three items are included: 1) A new effective digital FM demodulation algorithm has been presented; 2) Carrier and PCM code synchronization techniques have been explored and a new carrier deviation suppression algorithm has been proposed; 3) A prototype of PCM/FM digital receiver which is designed and implemented with high speed ADC, dedicated DDC and FPGA has been tested in the lab. Because typical DDC method is hard to receive wideband signals, the second topic of the thesis is about effective wideband DDC implementation structures. Four structures have been studied, which can overcome difficulties of typical DDC method effectively. Design of all digital high data rate transmission transceivers is the key techniques of the TDRSS systems. The third topic of the thesis is concerned with the problem designing 800Mbps 8PSK receiver, two main items are included: 1) Implementation scheme and 8PSK demodulation algorithms have been proposed, which are performed in the frequency domain in parallel and verified by computer simulations; 2) A prototype of 8PSK receiver which is designed and implemented with super high speed A/D converter and high performance FPGA has been tested in the lab. The fourth topic of the thesis is about digital IF modulation and frequency synthesis techniques, three items are involved: 1) A four channel multimode digital IF modulator has been implemented based on the ICS-564A DAC card; 2) Implementation scheme of 800Mbps 8PSK wideband digital modulator has been put forward. A prototype which is designed with high performance FPGA and super high speed D/A converter has been tested in the lab; 3) A wideband low phase noise frequency synthesizer has been implemented with an improved DDS+PLL hybrid synthesis techniques, which can cover the S,L and C bands at one time.
The main creative points in this thesis are as follows:
1) In the research of the PCM/FM IF digital receiver, a high effective FM demodulation algorithm has been presented, which performs phase discrimination with CORDIC algorithm and then first order differential frequency discrimination to the phase discriminated results and is suited to be realized with FPGA in the form of multi-stage streamlined structure.
2) Carrier and timing synchronization techniques of the PCM/FM IF digital receiver have been studied. A new carrier deviation suppression algorithm has been proposed that can perform envelope detection with a slip window and then subtract detected results from the received signals, which consumes little amount of calculations and is adaptive to carrier variation.
3) A PCM/FM IF digital receiver has been implemented with IF sampling ADC, dedicated DDC and FPGA, which has better performances and is verified by experimental results.
4) Four effective wideband DDC implementation structure have been researched: mixer postpositional structure, the minimum common multiples structure, once frequency transfer structure and double frequency transfer structure, which can decrease multiplication speed of filtering and mixing in effect.
5) Implementation scheme and demodulation algorithms of 800Mbps 8PSK receiver have been presented which are performed in the frequency domain in parallel and verified by computer simulations.
6) An 800Mbps 8PSK receiver has been implemented with super high speed A/D converter and high performance FPGA, which can demodulate 8PSK signals correctly.
7) Design scheme of 800Mbps 8PSK IF modulator has been presented. A prototype has been implemented with high performance FPGA and super high speed D/A converter, which has better EVM performances verified by the experimental results.
8) A wideband low phase noise frequency synthesizer has been implemented with an improved DDS+PLL hybrid frequency synthesize technique which has better performances and can cover the L, S, C bands at one time.
引文
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