低功耗逐次逼近模数转换器的研究与设计
摘要
逐次逼近模数转换器(ADC)具有中等转换精度和中等转换速度,采用CMOS工艺实现可以保证较小的芯片面积和低功耗,而且易于实现多路转换,在精度、速度、功耗和成本方面具有综合优势,被广泛应用于工业控制、医疗仪器以及微处理器辅助模数转换接口等领域。
论文工作设计了一个电源电压为2.5V,精度为12位,速度为500kS/s的低功耗逐次逼近ADC。电路采用单端轨到轨输入,并具有省电模式。
研究工作主要分为三个部分:①研究设计了一个分段电容式数模转换器(DAC),高端低端各6位,共有128个单位电容,减小了芯片面积,降低了动态功耗,而且高3位采用温度计编码,保证了DAC高位的单调性;分段电容阵列的版图采用共中心的对称布局,以提高电容的匹配精度。②对多级结构比较器进行了研究设计。比较器由三级前置放大器和一级锁存器组成,根据每级前置放大器的位置不同,对它们的增益、带宽、功耗进行了优化,每级前置放大器和模拟缓冲级电路的设计也减小了回程噪声的影响;比较器的设计应用了失调校准技术。仿真结果显示,该比较器可以有效消除10mV输入失调,能够在10MHz速度下分辨0.2mV输入电压,功耗只有600uW,达到了设计要求。③对控制电路进行了研究设计。采用分模块设计方法,使用verilog-HDL描述、自动综合、布局布线生成,能够控制模拟部分完成逐次逼近过程,并可以根据片选信号时间长短控制芯片进入省电模式或者工作模式。
论文工作在完成ADC电路设计仿真的基础上,完成了整个电路的物理版图设计、后仿真及芯片的测试。该逐次逼近ADC采用UMC 0.18um混合信号CMOS工艺设计制造,芯片面积为1.4mm×1mm。实测结果显示,在500kS/s下,其SNDR为63.13dB,即ENOB为10.5位,|DNL|小于2LSB,|INL|小于4LSB,功耗为1.2mW。
Successive approximation analog-to-digital converters (ADCs) have medium resolution and medium speed, small chip area and low power consumption can also be achieved in CMOS process. Moreover, it is convenient to make multi-channel conversion. Due to their mixed advantages in resolution, speed, power and cost, successive approximation ADCs are widely applied in industry controlling, medical instruments, auxiliary analog-to-digital interfaces of micro-processors and so on.
A 2.5V, 12bit, 500kS/s low-power successive approximation ADC is designed in this thesis, which adopts single rail-to-rail input and has power-down mode.
Study work can be categorized into 3 parts:①A segmented capacitive digital-to- analog converter (DAC) is designed with 2 separated 6-bit arrays which consist of 128 unit capacitors in all, resulting in smaller chip area and lower dynamic power. Moreover, thermometer coding is applied to the top 3 bits, ensuring the DAC’s monotonicity. Common centroid geometry is introduced in the layout to improve matching property.②A multi-stage comparator is designed, which is composed of 3 pre-amplifiers and a latch. Each pre-amplifier is optimized according to its position, the design of them and the analog buffer has already taken kickback noise into consideration. An offset cancellation technique is applied too. Simulation results show that, the proposed comparator can distinguish 0.2mV input with 10mV offset at 10MHz, while its power is 600uW.③The control circuit is designed in several modules, which is described in verilog-HDL, synthesized, placed and routed automatically. This digital block coordinates analog circuits to finish the successive approximation, and switches the chip into power-down mode or work mode.
After circuit design and simulation, the physical layout design, post-simulation and chip measurement are also finished. The proposed ADC is designed and fabricated in UMC 0.18um Mixed Mode CMOS process, occupying 1.4mm×1mm. Measurement results show that, its SNDR achieves 63.13dB at 500kS/s, thus ENOB is 10.5bit, and |DNL| is less than 2LSB, |INL| is less than 4LSB, with overall power only 1.2mW.
论文工作设计了一个电源电压为2.5V,精度为12位,速度为500kS/s的低功耗逐次逼近ADC。电路采用单端轨到轨输入,并具有省电模式。
研究工作主要分为三个部分:①研究设计了一个分段电容式数模转换器(DAC),高端低端各6位,共有128个单位电容,减小了芯片面积,降低了动态功耗,而且高3位采用温度计编码,保证了DAC高位的单调性;分段电容阵列的版图采用共中心的对称布局,以提高电容的匹配精度。②对多级结构比较器进行了研究设计。比较器由三级前置放大器和一级锁存器组成,根据每级前置放大器的位置不同,对它们的增益、带宽、功耗进行了优化,每级前置放大器和模拟缓冲级电路的设计也减小了回程噪声的影响;比较器的设计应用了失调校准技术。仿真结果显示,该比较器可以有效消除10mV输入失调,能够在10MHz速度下分辨0.2mV输入电压,功耗只有600uW,达到了设计要求。③对控制电路进行了研究设计。采用分模块设计方法,使用verilog-HDL描述、自动综合、布局布线生成,能够控制模拟部分完成逐次逼近过程,并可以根据片选信号时间长短控制芯片进入省电模式或者工作模式。
论文工作在完成ADC电路设计仿真的基础上,完成了整个电路的物理版图设计、后仿真及芯片的测试。该逐次逼近ADC采用UMC 0.18um混合信号CMOS工艺设计制造,芯片面积为1.4mm×1mm。实测结果显示,在500kS/s下,其SNDR为63.13dB,即ENOB为10.5位,|DNL|小于2LSB,|INL|小于4LSB,功耗为1.2mW。
Successive approximation analog-to-digital converters (ADCs) have medium resolution and medium speed, small chip area and low power consumption can also be achieved in CMOS process. Moreover, it is convenient to make multi-channel conversion. Due to their mixed advantages in resolution, speed, power and cost, successive approximation ADCs are widely applied in industry controlling, medical instruments, auxiliary analog-to-digital interfaces of micro-processors and so on.
A 2.5V, 12bit, 500kS/s low-power successive approximation ADC is designed in this thesis, which adopts single rail-to-rail input and has power-down mode.
Study work can be categorized into 3 parts:①A segmented capacitive digital-to- analog converter (DAC) is designed with 2 separated 6-bit arrays which consist of 128 unit capacitors in all, resulting in smaller chip area and lower dynamic power. Moreover, thermometer coding is applied to the top 3 bits, ensuring the DAC’s monotonicity. Common centroid geometry is introduced in the layout to improve matching property.②A multi-stage comparator is designed, which is composed of 3 pre-amplifiers and a latch. Each pre-amplifier is optimized according to its position, the design of them and the analog buffer has already taken kickback noise into consideration. An offset cancellation technique is applied too. Simulation results show that, the proposed comparator can distinguish 0.2mV input with 10mV offset at 10MHz, while its power is 600uW.③The control circuit is designed in several modules, which is described in verilog-HDL, synthesized, placed and routed automatically. This digital block coordinates analog circuits to finish the successive approximation, and switches the chip into power-down mode or work mode.
After circuit design and simulation, the physical layout design, post-simulation and chip measurement are also finished. The proposed ADC is designed and fabricated in UMC 0.18um Mixed Mode CMOS process, occupying 1.4mm×1mm. Measurement results show that, its SNDR achieves 63.13dB at 500kS/s, thus ENOB is 10.5bit, and |DNL| is less than 2LSB, |INL| is less than 4LSB, with overall power only 1.2mW.
引文
[1] Zhimin Zhou, Bedabrata Pain and Eric R. Fossum, “CMOS Active Pixel Sensor with On-Chip Successive Approximation Analog-to-Digital Converter”, IEEE Transactions on Electron Devices, Volume 44, Issue 10, Oct. 1997, Page(s):1759-1763
[2] Kwang-Bo Cho, Alexander Krymski and Eric R. Fossum, “A 3-Pin 1.5V 550uW 176x144 Self-Clocked CMOS Active Pixel Image Sensor”, ISLPED’01, Aug. 6-7, 2001, Page(s):316- 321
[3] Michael D. Scott, Bernhard E. Boser and Kristofer S. J. Pister, “An Ultralow-Energe ADC for Smart Dust”, IEEE Journal of Solid-State Circuits, Volume 38, Issue 7, July 2003, Page(s):1123-1129
[4] H. P. Le, J. Singh, L. Hiremath, V. Mallapur and A. Stojcevski, “Ultra-low-power Variable-resolution successive approximation ADC for Biomedical Application”, Electronics Letters, Volume 41, Issue 11, May 26th, 2005
[5] Wayne Talley, “利用 SAR ADC 降低成本、扩展应用”, 电子产品世界, 2003.8 下半月
[6] R. Jacob Baker. CMOS Circuit Design, Layout, and Simulation, Second Edition, Wiley-IEEE Press, 2003
[7] Anon. ADC0816 ADC0817 8-Bit MuP Compatible AD Converters with 16-Channel Multiplexer. National Semiconductor Data Sheets, 1994
[8] Hans-ulrich Post and Klaus Waldschmidt. A High-Speed NMOS A/D Converter with a Current Source Array. IEEE Journal of Solid-State Circuits, 1980, 15(3): 295-301
[9] Siamak Mortezapour and Edward K. F. Lee. A 1-V, 8-Bit Successive Approximation ADC in Standard CMOS Process. IEEE Journal of Solid-State Circuits, 2000, 35(4): 642-646
[10] James L. McCreary and Paul R. Gray. All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques - Part I. IEEE Journal of Solid-State Circuits, 1975, 10(6): 371-379
[11] Jaejin Park, Ho-Jin Park, Jae-Whui Kim, Sangnam Seo and Philip Chung. A 1mW 10-bit 500KSPS SAR A/D Converter. ISCAS IEEE International Symposium on Circuits and System, Geneva, Switzerland, 2000: 581-584
[12] Jens Sauerbrey, Doris Schmitt-Landsiedel and Roland Thewes. A 0.5-V 1-uW Successive Approximation ADC. IEEE Journal of Solid-State Circuits, 2003, 38(7): 1261-1265
[13] Takeshi Yoshida, Miho Akagi, Mamoru Sasaki and Atsushi Iwata. A 1V Supply Successive Approximation ADC with rail-to-rail input voltage range. IEEE, 2005: 192-195
[14] Harald Neubauer, Thomas Desel and Hans Hauer. A Successive Approximation A/D Converter with 16bit 200kS/s in 0.6um CMOS using Selfcalibration and Low Power Techniques. IEEE, 2001: 859-862
[15] Eugenio Culurciello and Andreas Andreou. An 8-bit, 1mW Successive Approximation ADC in SOI CMOS. IEEE, 2003: 301-304
[16] G. Mazza, A. Rivetti, G. Anelli, F. Anghinolfi, M. I. Martinez and F. Rotondo. A 32-Channel, 0.25 um CMOS ASIC for the Readout of the Silicon Drift Detectors of the ALICE Experiment. IEEE Transactions on Nuclear Science, 2004, 51(5): 1942-1947
[17] Ricardo E. Suárez, Paul R. Gray and David A. Hodges. All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part II. IEEE Journal of Solid-State Circuits, 1975, 10(6): 379-385
[18] Bahram Fotouhi and David A. Hodges. High-Resolution A/D Conversion in MOS/LSI. IEEE Journal of Solid-State Circuits, 1979, 14(6): 920-926
[19] Hae-Seung Lee, David A. Hodges and Paul R. Gray. A Self-Calibrating 15 Bit CMOS A/D Converter. IEEE Journal of Solid-State Circuits, 1984, 19(6): 813-819
[20] Tetsuya Iida, Junkei Gotoh, Akihiro Nishizuka and Hitoshi Hara. A CMOS 10Bit Accuracy and 5uS Speed AD Converter. IEEE Custom Integrated Circuits Conference, 1988: 9.2.1-9.2.4
[21] 蔡俊, 徐美华, 冉峰. 10 位逐次逼近型 A/D 转换器的芯片设计. 半导体技术, 2004, 29(4): 73-76
[22] Kh. Hadidi, Vincent S. Tso and Gabor C. Temes. An 8-b 1.3-MHz Successive-Approximation A/D Converter. IEEE Journal of Solid-State Circuits, 1990, 25(3): 880-885
[23] Kh. Hadidi, Vincent S. Tso and G.C. Temes. Fast Successive-Approximation A/D Converters. IEEE Custom Integrated Circuits Conference, 1990: 6.1.1-6.1.4
[24] Harri Lampinen and Olli Vainio. A New Dual-Mode Data Compressing A/D Converter. IEEE International Symposium on Circuits and Systems, 1997, 429-432
[25] Mehdi Banihashemi, Khayrollah Hadidi and Abdollah Khoei. A Low-Power,Small-Size 10-Bit Successive- Approximation ADC. IEICE Trans. Fundamentals, 2005, E88-A(4): 996-1006
[26] Satomi Ogawa and Kenzo Watanabe. A Switched-Capacitor Successive-Approximation Analog -to-Digital Converter. IEEE 1990: 1577-1580
[27] Satomi Ogawa and Kenzo Watanabe. A Switched- Capacitor Successive-Approximation A/D Converter. IEEE Transactions on Instrumentation and Measurement, 1993, 42(4): 847-853
[28] S.P. Singh, A Prabhakar, and A. B. Bhattcharyya. C-2C Ladder-Based D/A Converters for PCM Codecs. IEEE Journal of Solid-State Circuits, 1987, 22(6): 1197-1200
[29] Lin Cong and William C. Black. A new charge redistribution D/A and A/D converter technique pseudo C-2C ladder. Proc. 43rd IEEE Midwest Symp. On Circuits and Systems, 2000: 498-501
[30] Jianhua Gan and Jacob Abraham. A Non-Binary Capacitor Array Calibration Circuit with22-bit Accuracy in Successive Approximation Analog-to-Digital Converters. IEEE, 2002: I567-I570
[31] Khosrov Dabbagh-Sadeghipour, Khayrollah Hadidi and Abdollah Khoei. A New Architecture for Area and Power Efficient High Conversion Rate Successive Approximation ADCs. IEEE, 2004: 253-256
[32] Sanjay M. Bhandari and Sudhir Aggarwal. A successive double-bit approximation technique for analog digital conversion. IEEE Transactions on Circuits and Systems, 1990, 37(6): 856-858
[33] Christopher M. Webster and Donald T. comer. An Enhanced Successive-Approximation Circuit for A/D Conversion. IEEE Custom Integrated Circuits Conference, 1993: 28.2.1-28.2.4
[34] Jannik Hammel Nielsen, Pietro Andreani, Piero Malcovati and Andrea Baschirotto. Technology Scaling Impact on Embedded ADC Design for Telecom Receivers. IEEE, 2005: 4614-4617
[35] Brian P. Ginsburg and Anantha P. Chandrakasan. An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC. IEEE, 2005: 184-187
[36] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, “CMOS Data Converters for Communications”, Kluwer Academic Publishers, 2002
[37] Jiren Yuan and Christer Svensson, “A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2-um CMOS”, IEEE Journal of Solid-State Circuits, vol. 29, No. 8, Aug 1994
[38] Behzad Razavi and Bruce A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators”, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec 1992
[39] Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design (Seconde Edition)”, Publishing House of Electronics Industry, 2002
[40] Jianhua Gan, Shouli Yan and Jacob Abraham, “Effects of Noise and Nonlinearity on the Calibration of a Non-Binary Capacitor Array in a Successive Approximation Analog-to-Digital Converter”, 2004 IEEE
[41] Gilbert Promitzer, “12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s”, IEEE Journal of Solid-State Circuits, vol. 36, No. 7, Jul 2001
[42] Figueiredo P M, Vital J C. Low kickback noise techniques for CMOS latched comparators [A]. IEEE International Symposium on Circuits and Systems [C]. Vancouver, British Columbia, Canada, 2004. I - 537-40 Vol.1
[2] Kwang-Bo Cho, Alexander Krymski and Eric R. Fossum, “A 3-Pin 1.5V 550uW 176x144 Self-Clocked CMOS Active Pixel Image Sensor”, ISLPED’01, Aug. 6-7, 2001, Page(s):316- 321
[3] Michael D. Scott, Bernhard E. Boser and Kristofer S. J. Pister, “An Ultralow-Energe ADC for Smart Dust”, IEEE Journal of Solid-State Circuits, Volume 38, Issue 7, July 2003, Page(s):1123-1129
[4] H. P. Le, J. Singh, L. Hiremath, V. Mallapur and A. Stojcevski, “Ultra-low-power Variable-resolution successive approximation ADC for Biomedical Application”, Electronics Letters, Volume 41, Issue 11, May 26th, 2005
[5] Wayne Talley, “利用 SAR ADC 降低成本、扩展应用”, 电子产品世界, 2003.8 下半月
[6] R. Jacob Baker. CMOS Circuit Design, Layout, and Simulation, Second Edition, Wiley-IEEE Press, 2003
[7] Anon. ADC0816 ADC0817 8-Bit MuP Compatible AD Converters with 16-Channel Multiplexer. National Semiconductor Data Sheets, 1994
[8] Hans-ulrich Post and Klaus Waldschmidt. A High-Speed NMOS A/D Converter with a Current Source Array. IEEE Journal of Solid-State Circuits, 1980, 15(3): 295-301
[9] Siamak Mortezapour and Edward K. F. Lee. A 1-V, 8-Bit Successive Approximation ADC in Standard CMOS Process. IEEE Journal of Solid-State Circuits, 2000, 35(4): 642-646
[10] James L. McCreary and Paul R. Gray. All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques - Part I. IEEE Journal of Solid-State Circuits, 1975, 10(6): 371-379
[11] Jaejin Park, Ho-Jin Park, Jae-Whui Kim, Sangnam Seo and Philip Chung. A 1mW 10-bit 500KSPS SAR A/D Converter. ISCAS IEEE International Symposium on Circuits and System, Geneva, Switzerland, 2000: 581-584
[12] Jens Sauerbrey, Doris Schmitt-Landsiedel and Roland Thewes. A 0.5-V 1-uW Successive Approximation ADC. IEEE Journal of Solid-State Circuits, 2003, 38(7): 1261-1265
[13] Takeshi Yoshida, Miho Akagi, Mamoru Sasaki and Atsushi Iwata. A 1V Supply Successive Approximation ADC with rail-to-rail input voltage range. IEEE, 2005: 192-195
[14] Harald Neubauer, Thomas Desel and Hans Hauer. A Successive Approximation A/D Converter with 16bit 200kS/s in 0.6um CMOS using Selfcalibration and Low Power Techniques. IEEE, 2001: 859-862
[15] Eugenio Culurciello and Andreas Andreou. An 8-bit, 1mW Successive Approximation ADC in SOI CMOS. IEEE, 2003: 301-304
[16] G. Mazza, A. Rivetti, G. Anelli, F. Anghinolfi, M. I. Martinez and F. Rotondo. A 32-Channel, 0.25 um CMOS ASIC for the Readout of the Silicon Drift Detectors of the ALICE Experiment. IEEE Transactions on Nuclear Science, 2004, 51(5): 1942-1947
[17] Ricardo E. Suárez, Paul R. Gray and David A. Hodges. All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part II. IEEE Journal of Solid-State Circuits, 1975, 10(6): 379-385
[18] Bahram Fotouhi and David A. Hodges. High-Resolution A/D Conversion in MOS/LSI. IEEE Journal of Solid-State Circuits, 1979, 14(6): 920-926
[19] Hae-Seung Lee, David A. Hodges and Paul R. Gray. A Self-Calibrating 15 Bit CMOS A/D Converter. IEEE Journal of Solid-State Circuits, 1984, 19(6): 813-819
[20] Tetsuya Iida, Junkei Gotoh, Akihiro Nishizuka and Hitoshi Hara. A CMOS 10Bit Accuracy and 5uS Speed AD Converter. IEEE Custom Integrated Circuits Conference, 1988: 9.2.1-9.2.4
[21] 蔡俊, 徐美华, 冉峰. 10 位逐次逼近型 A/D 转换器的芯片设计. 半导体技术, 2004, 29(4): 73-76
[22] Kh. Hadidi, Vincent S. Tso and Gabor C. Temes. An 8-b 1.3-MHz Successive-Approximation A/D Converter. IEEE Journal of Solid-State Circuits, 1990, 25(3): 880-885
[23] Kh. Hadidi, Vincent S. Tso and G.C. Temes. Fast Successive-Approximation A/D Converters. IEEE Custom Integrated Circuits Conference, 1990: 6.1.1-6.1.4
[24] Harri Lampinen and Olli Vainio. A New Dual-Mode Data Compressing A/D Converter. IEEE International Symposium on Circuits and Systems, 1997, 429-432
[25] Mehdi Banihashemi, Khayrollah Hadidi and Abdollah Khoei. A Low-Power,Small-Size 10-Bit Successive- Approximation ADC. IEICE Trans. Fundamentals, 2005, E88-A(4): 996-1006
[26] Satomi Ogawa and Kenzo Watanabe. A Switched-Capacitor Successive-Approximation Analog -to-Digital Converter. IEEE 1990: 1577-1580
[27] Satomi Ogawa and Kenzo Watanabe. A Switched- Capacitor Successive-Approximation A/D Converter. IEEE Transactions on Instrumentation and Measurement, 1993, 42(4): 847-853
[28] S.P. Singh, A Prabhakar, and A. B. Bhattcharyya. C-2C Ladder-Based D/A Converters for PCM Codecs. IEEE Journal of Solid-State Circuits, 1987, 22(6): 1197-1200
[29] Lin Cong and William C. Black. A new charge redistribution D/A and A/D converter technique pseudo C-2C ladder. Proc. 43rd IEEE Midwest Symp. On Circuits and Systems, 2000: 498-501
[30] Jianhua Gan and Jacob Abraham. A Non-Binary Capacitor Array Calibration Circuit with22-bit Accuracy in Successive Approximation Analog-to-Digital Converters. IEEE, 2002: I567-I570
[31] Khosrov Dabbagh-Sadeghipour, Khayrollah Hadidi and Abdollah Khoei. A New Architecture for Area and Power Efficient High Conversion Rate Successive Approximation ADCs. IEEE, 2004: 253-256
[32] Sanjay M. Bhandari and Sudhir Aggarwal. A successive double-bit approximation technique for analog digital conversion. IEEE Transactions on Circuits and Systems, 1990, 37(6): 856-858
[33] Christopher M. Webster and Donald T. comer. An Enhanced Successive-Approximation Circuit for A/D Conversion. IEEE Custom Integrated Circuits Conference, 1993: 28.2.1-28.2.4
[34] Jannik Hammel Nielsen, Pietro Andreani, Piero Malcovati and Andrea Baschirotto. Technology Scaling Impact on Embedded ADC Design for Telecom Receivers. IEEE, 2005: 4614-4617
[35] Brian P. Ginsburg and Anantha P. Chandrakasan. An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC. IEEE, 2005: 184-187
[36] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, “CMOS Data Converters for Communications”, Kluwer Academic Publishers, 2002
[37] Jiren Yuan and Christer Svensson, “A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2-um CMOS”, IEEE Journal of Solid-State Circuits, vol. 29, No. 8, Aug 1994
[38] Behzad Razavi and Bruce A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators”, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec 1992
[39] Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design (Seconde Edition)”, Publishing House of Electronics Industry, 2002
[40] Jianhua Gan, Shouli Yan and Jacob Abraham, “Effects of Noise and Nonlinearity on the Calibration of a Non-Binary Capacitor Array in a Successive Approximation Analog-to-Digital Converter”, 2004 IEEE
[41] Gilbert Promitzer, “12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s”, IEEE Journal of Solid-State Circuits, vol. 36, No. 7, Jul 2001
[42] Figueiredo P M, Vital J C. Low kickback noise techniques for CMOS latched comparators [A]. IEEE International Symposium on Circuits and Systems [C]. Vancouver, British Columbia, Canada, 2004. I - 537-40 Vol.1
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