基于硅通孔技术的三维集成电路设计与分析
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摘要
计算机与信息技术的空前发展要求超大规模集成（Very Large Scale Integrated,VLSI）电路具有不断增强的功能与性能，同时又具有最低的价格与功耗。对VLSI电路进行激进缩小可以满足这一要求，但也导致了一个非常严重的问题，即互连传输延时与交互干扰噪声取代门延时，成为决定电路性能与功耗的关键因素。另外，随着芯片功能的增强，片内集成的晶体管数目急剧增加，体积与功耗持续上升，已经逼近二维（Two Dimensional,2-D）器件技术的极限，传统平面芯片的研发与生产都遭遇了难以克服的技术瓶颈。三维集成作为一种系统级架构的新方法，内部含有多个平面器件层的层叠，并经由硅通孔（Through Silicon Vis, TSV）在垂直方向实现相互连接，大幅度缩小芯片尺寸，提高芯片的晶体管密度，改善层间电气互联性能，提升芯片运行速度，降低芯片的功耗，成为未来纳米集成电路发展的重要趋势。本文从随机互连线长的分布模型入手，对片上系统（System on Chip,SoC）全局信号布线网络的设计约束进行了深入分析，定义了三维集成电路（ThreeDimensional Integrated Circuits,3-D ICs）全局互连设计空间；基于TSV电热模型，研究了TSV电热传输效应对互连传输延时、功耗密度与有源层温度分布特性的影响，提出了相应的设计优化方法；针对传统铜互连技术面临的物理局限性，提出将碳纳米管应用于3D ICs设计，并探讨了这一新型材料在未来纳米集成电路中应用特性。本文的主要研究成果如下：
1.基于随机多层互连分布模型，对3-D ICs的互连线长分布进行合理预测。根据已有随机线长分布，分析了吉规模片上系统（Giga-scale SoC：GSoC）在布线面积需求、布线带宽要求与串扰噪声约束下的全局互连设计空间。通过对包含不同硅有源层的SoC全局设计空间的比较分析，从设计可靠性与电路性能的角度验证了3-D集成技术在吉规模互连电路设计中的巨大优势，为3-D集成技术应用于未来集成电路设计提供了有利的技术支持。
2.分析了TSV电阻-电容（Resistance-Capacitance, RC）寄生效应对SoC互连性能及电路功耗影响，并推导了插入缓冲器的三维互连线延时与功耗的解析模型。对不同规模的互连电路模拟结果显示，TSV RC效应将导致互连延时平均增加10%，互连功耗密度平均提高21%；电路规模越小，TSV影响愈加显著。在3-D SoC前端设计中，包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能。
3.分析了TSV物理尺寸与布局位置对异质3-D ICs的互连时序性能与信号完整性影响，并提出了一个同步改善互连延时与信号反射系数的TSV插入优化算法。与传统TSV等分连线布局算法的模拟比较结果显示，该TSV插入优化算法导致互连延时平均降低了49.96%，反射系数平均减小62.28%，且层间阻抗差异越大，延时优化效果愈加显著，它可以应用于未来3-D ICs的计算机辅助设计。
4.采用一维等效热阻方程，建立了考虑TSV传导的3-D ICs热传输解析模型，并分析TSV密度与材质、散热片等效热阻、后端互连热导率及衬底厚度等设计因素对3-D芯片有源层温度分布特性的影响，提出改善散热片等效热阻的优化设计策略。仿真结果表明，降低散热片热阻是应对功耗密度与峰值温度急剧上升，保证3-D芯片可靠工作的有效方式。该热传输模型能够应用于3-D ICs早期电路开发与版图布局，为芯片设计者提供热设计参考与指导。
5.对单壁碳纳米管束(Single Wall Carbon Nanotube, SWCNT bundle)连线的电阻-电感-电容（Resistance-Inductance-Capacitance, RLC）参数进行提取与分析，建立了与现有电路仿真软件相兼容的分布参数等效电路模型。在不同工艺节点下，对采用铜互连与SWCNT Bundle连线的3-D ICs各层互连线性能进行分析比较。Hspice仿真结果显示，SWCNT Bundle连线有效地降低了局部互连线延时，优化连线尺寸；对于包含层间TSV与插入缓冲器的中间层和全局互连线，SWCNT bundle连线的传输延时可以只达到铜互连的45.49%与51.84%。具有良好电热传输特性的碳纳米管是未来纳米集成电路互连线的一种很有前景材料。
The unprecedented development of computer and information technology isdemanding Very-Large-Scale-Integration (VLSI) circuits with increasing functionalityand performance at minimum cost and power consumption. The feature size oftransistor is being aggressively shrunk to meet this demand. However, in turn, this hasintroduced some very serious problems. Interconnect propagation delay and crosstalkdistortions replace the gate delay and come to be the dominant factor limiting overallperformance and power dissipation. Additionally, with the enhancement of the chipfunctionality, the number of integrated transistors is dramatically increased, the chipsize and power dissipation continually rise and has gradually approachedtwo-dimensional (2-D) device technology limit. The production and fabrication of thetraditional plane semiconductor process encounter the insurmountable technicalbottleneck. Three dimensional (3-D) or vertical integration is emerging as a promisingsolution that can form highly integration system by vertically stacking and providecommunication among device or functional blocks within an IC with inter-planethrough silicon via (TSV), thereby providing reduced chip size, high device integrationdensity, enhanced interconnectivity, high bandwidth and low power. This thesis embarkson the a stochastic wire length distribution model, establishes a global interconnectdesign window for gig scale3-D system on chip (GSoC) by evaluating the designconstraints of global signal network; Based on3-D TSV model, it analyzes the impactof TSV electro-thermal effect on3-D interconnect propagation delay, power density andactive-layers temperature distribution; To coop with the physical limitation of traditionCopper (Cu) interconnect, it investigates the feasibility of using Carbon Nanotubes(CNTs) for interconnects application in3-D ICs. The main studies and contribution ofthis dissertation are as follows.
1. Based on a stochastic wire length distributed model, the interconnect distributionof3D ICs is predicted exactly. Using the results of this model, a global interconnectdesign window for gig scale SoC is established by evaluating the constraints of wiringresource, wiring bandwidth and wiring noise. In comparison to a2D IC, the designwindow expands for a3D IC to improve the design reliability and system performance,further supporting3D ICs application in future integrated circuits design.
2. After analysis of the impact of TSV parasitic resistance-capacitance (RC)parameters on interconnect performance and circuit power dissipation, closed-formdelay and power consumption expressions for buffered interconnect used in3D IC are presented. Comparative results with3D net without TSV in various cases show thatTSV RC effect has huge impact on delay and power of3D ICs that leading to extraoverhead of on average10%for maximum delay and21%for power consumption.Therefore, it is crucial to correctly establish a TSV-aware3D interconnect model in3DICs front-end design.
3. Analyzing the impact of TSV size and placement on the interconnect timingperformance and signal integrity, an approach for TSV insertion in3D ICs to minimizethe propagation delay with consideration to signal reflection is presented. Simulationresults demonstrate that our approach in generally can result in a49.96%improvementin average delay, a62.28%decrease in the reflection coefficient, and the optimizationfor delay can be more effective for higher non-uniform inter-plane interconnects. Theproposed approach can be integrated into the TSV-aware design and optimization toolsfor3-D circuits to enhance system performance.
4. Based a one-dimensional (1-D) heat transfer equation, an analytical heat transfermodel for3D ICs incorporating TSV effect is developed. The impact of TSV insertion,heat sink thermal resistance, thermal conductivity of back of end line and substratethickness on the thermal performance of stacked3D ICs are analyzed, Simulationresults demonstrate heat sink thermal resistance improvement is a significant way tocope with the challenge in3D-ICs thermal management. The proposed heat transfermodel can be integrated into3D ICs early-stage design and layout tools to fully takeadvantage of the electrical benefits without significant exacerbation of the thermalmanagement challenge.
5. Compact equivalent circuit models for Single-Walled Carbon Nanotubes(SWCNTs) are described, and the performance of SWCNT interconnects is evaluatedand compared with traditional Cu interconnects at different interconnect levels (local,intermediate, and global) for TSV based3-D ICs. It is shown that at local level, CNTbundle interconnects exhibit lower signal delay and smaller optimal wire size. Atintermediate and global levels, delay improvement becomes more significant withtechnology scaling and increasing wire lengths. For1mm intermediate and10mm globallevel interconnects, the delay of SWCNT bundles can reach45.49%and51.84%of thatof Cu wires, respectively.
1.基于随机多层互连分布模型，对3-D ICs的互连线长分布进行合理预测。根据已有随机线长分布，分析了吉规模片上系统（Giga-scale SoC：GSoC）在布线面积需求、布线带宽要求与串扰噪声约束下的全局互连设计空间。通过对包含不同硅有源层的SoC全局设计空间的比较分析，从设计可靠性与电路性能的角度验证了3-D集成技术在吉规模互连电路设计中的巨大优势，为3-D集成技术应用于未来集成电路设计提供了有利的技术支持。
2.分析了TSV电阻-电容（Resistance-Capacitance, RC）寄生效应对SoC互连性能及电路功耗影响，并推导了插入缓冲器的三维互连线延时与功耗的解析模型。对不同规模的互连电路模拟结果显示，TSV RC效应将导致互连延时平均增加10%，互连功耗密度平均提高21%；电路规模越小，TSV影响愈加显著。在3-D SoC前端设计中，包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能。
3.分析了TSV物理尺寸与布局位置对异质3-D ICs的互连时序性能与信号完整性影响，并提出了一个同步改善互连延时与信号反射系数的TSV插入优化算法。与传统TSV等分连线布局算法的模拟比较结果显示，该TSV插入优化算法导致互连延时平均降低了49.96%，反射系数平均减小62.28%，且层间阻抗差异越大，延时优化效果愈加显著，它可以应用于未来3-D ICs的计算机辅助设计。
4.采用一维等效热阻方程，建立了考虑TSV传导的3-D ICs热传输解析模型，并分析TSV密度与材质、散热片等效热阻、后端互连热导率及衬底厚度等设计因素对3-D芯片有源层温度分布特性的影响，提出改善散热片等效热阻的优化设计策略。仿真结果表明，降低散热片热阻是应对功耗密度与峰值温度急剧上升，保证3-D芯片可靠工作的有效方式。该热传输模型能够应用于3-D ICs早期电路开发与版图布局，为芯片设计者提供热设计参考与指导。
5.对单壁碳纳米管束(Single Wall Carbon Nanotube, SWCNT bundle)连线的电阻-电感-电容（Resistance-Inductance-Capacitance, RLC）参数进行提取与分析，建立了与现有电路仿真软件相兼容的分布参数等效电路模型。在不同工艺节点下，对采用铜互连与SWCNT Bundle连线的3-D ICs各层互连线性能进行分析比较。Hspice仿真结果显示，SWCNT Bundle连线有效地降低了局部互连线延时，优化连线尺寸；对于包含层间TSV与插入缓冲器的中间层和全局互连线，SWCNT bundle连线的传输延时可以只达到铜互连的45.49%与51.84%。具有良好电热传输特性的碳纳米管是未来纳米集成电路互连线的一种很有前景材料。
The unprecedented development of computer and information technology isdemanding Very-Large-Scale-Integration (VLSI) circuits with increasing functionalityand performance at minimum cost and power consumption. The feature size oftransistor is being aggressively shrunk to meet this demand. However, in turn, this hasintroduced some very serious problems. Interconnect propagation delay and crosstalkdistortions replace the gate delay and come to be the dominant factor limiting overallperformance and power dissipation. Additionally, with the enhancement of the chipfunctionality, the number of integrated transistors is dramatically increased, the chipsize and power dissipation continually rise and has gradually approachedtwo-dimensional (2-D) device technology limit. The production and fabrication of thetraditional plane semiconductor process encounter the insurmountable technicalbottleneck. Three dimensional (3-D) or vertical integration is emerging as a promisingsolution that can form highly integration system by vertically stacking and providecommunication among device or functional blocks within an IC with inter-planethrough silicon via (TSV), thereby providing reduced chip size, high device integrationdensity, enhanced interconnectivity, high bandwidth and low power. This thesis embarkson the a stochastic wire length distribution model, establishes a global interconnectdesign window for gig scale3-D system on chip (GSoC) by evaluating the designconstraints of global signal network; Based on3-D TSV model, it analyzes the impactof TSV electro-thermal effect on3-D interconnect propagation delay, power density andactive-layers temperature distribution; To coop with the physical limitation of traditionCopper (Cu) interconnect, it investigates the feasibility of using Carbon Nanotubes(CNTs) for interconnects application in3-D ICs. The main studies and contribution ofthis dissertation are as follows.
1. Based on a stochastic wire length distributed model, the interconnect distributionof3D ICs is predicted exactly. Using the results of this model, a global interconnectdesign window for gig scale SoC is established by evaluating the constraints of wiringresource, wiring bandwidth and wiring noise. In comparison to a2D IC, the designwindow expands for a3D IC to improve the design reliability and system performance,further supporting3D ICs application in future integrated circuits design.
2. After analysis of the impact of TSV parasitic resistance-capacitance (RC)parameters on interconnect performance and circuit power dissipation, closed-formdelay and power consumption expressions for buffered interconnect used in3D IC are presented. Comparative results with3D net without TSV in various cases show thatTSV RC effect has huge impact on delay and power of3D ICs that leading to extraoverhead of on average10%for maximum delay and21%for power consumption.Therefore, it is crucial to correctly establish a TSV-aware3D interconnect model in3DICs front-end design.
3. Analyzing the impact of TSV size and placement on the interconnect timingperformance and signal integrity, an approach for TSV insertion in3D ICs to minimizethe propagation delay with consideration to signal reflection is presented. Simulationresults demonstrate that our approach in generally can result in a49.96%improvementin average delay, a62.28%decrease in the reflection coefficient, and the optimizationfor delay can be more effective for higher non-uniform inter-plane interconnects. Theproposed approach can be integrated into the TSV-aware design and optimization toolsfor3-D circuits to enhance system performance.
4. Based a one-dimensional (1-D) heat transfer equation, an analytical heat transfermodel for3D ICs incorporating TSV effect is developed. The impact of TSV insertion,heat sink thermal resistance, thermal conductivity of back of end line and substratethickness on the thermal performance of stacked3D ICs are analyzed, Simulationresults demonstrate heat sink thermal resistance improvement is a significant way tocope with the challenge in3D-ICs thermal management. The proposed heat transfermodel can be integrated into3D ICs early-stage design and layout tools to fully takeadvantage of the electrical benefits without significant exacerbation of the thermalmanagement challenge.
5. Compact equivalent circuit models for Single-Walled Carbon Nanotubes(SWCNTs) are described, and the performance of SWCNT interconnects is evaluatedand compared with traditional Cu interconnects at different interconnect levels (local,intermediate, and global) for TSV based3-D ICs. It is shown that at local level, CNTbundle interconnects exhibit lower signal delay and smaller optimal wire size. Atintermediate and global levels, delay improvement becomes more significant withtechnology scaling and increasing wire lengths. For1mm intermediate and10mm globallevel interconnects, the delay of SWCNT bundles can reach45.49%and51.84%of thatof Cu wires, respectively.
引文
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