高速交换系统的研究及其专用集成电路的前端设计
摘要
这几年光纤通讯技术的飞速发展使得目前高速通讯网络性能的瓶颈集中在高速交换系统，研究、设计和制造高速交换系统对目前高速通讯网络有极其重要的意义。国际电信联盟(ITU—T)在制定宽带综合服务数据网络(B—ISDN)时采用异步传输模式(ATM)为其核心利基础。ATM实现高速通讯的一个重要方法是定义长度固定的信元作为数据传输的基本单位。由于信元长度固定，对信元的处理可以用ASIC实现，从而可以在交换机中实现高速信元交换，ATM交换因此得到广泛研究。其研究成果不仅对ATM网络本身，而且对其它需要高速交换的领域也有重要的借鉴意义。
本论文的目的是设计一个高速ATM交换系统，主要分成3个部分：
1)对目前交换系统进行分析研究。本论文定性分析了目前的分析交换系统，主要是时分交换系统和空分交换系统，以及空分交换结构对应缓存策略。由于目前光通讯技术的发展速度超过半导体工艺的进展速度，时分交换技术的分析结果表明它已经无法满足高速大规模交换系统的要求。
2)确定高速交换系统所采用的交换结构，对其进行详细的分析仿真。本论文将定量的分析和仿真空分交换结构和对应的调度算法，深入的了解Crossbar利MIN(包括EMIN)空分交换系统各方面的性能，分析利仿真输入缓存和输出缓存的缓存策略。由于输入缓存的队头阻塞使得高负载条件下输入缓存策略的交换系统各方面性能急剧下降，由此提出了克服输入缓存队头阻塞的改进方法，最后本文决定选用虚拟输出队列(VOQ)的输入缓存策略，并且研究了与虚拟输出队列相对应的iLQF(最长队列优先)和DPA(对角线优先)信元调度算法，为交换系统的ASIC设计提供依据。
3)根据前面的结论，设计出交换系统。在前面分析的基础上根据目前的条件，对一个空分交换系统各模块进行前端设计和仿真，由于交换系统的功能复杂，我们一部分将采用直接画原理图的方法进行设计，大部分将采用集成电路设计自动化的方法进行设计，即采用硬件设计语言Verilog—HDL进行设计，用Synopsys软件对设计进行综合，生成线路图，然后作门级电路仿真。在完成各模块的设计后，我们设计一个完整的ATM交换系统，输入模块采用虚拟输出队列的缓存策略，调度算法用对角线优先的DPA凋度算法，采用Crossbar的交换结构，然后对其进行仿真和计算，结果表明我们设计交换系统与目前光纤通讯网络的数据传输速度匹配。
ln these years the quick develop1nent of fabric com1nunication technology make the switch
systeln becoIni11g tI1e barrier of lnodern high speed communication network. So study, design and
lllanulhcture high speed switch system are very important fOr modern high speed communication
network. Asynchronous transfer mode (A1M) had been specified as the base of the broadband
integrated services digita1 network by international telecommunication union telecommunication
standardization sector (lTU-T). One important method of ATM to realize high speed data transfer
is using cell whose size is tixed. Because of it, ASlC cat1 deal with cell directIy. So ATM switch
cal1 switcl1 ceII at high speed, and study on A1'M switch is of great empl1asis in these years. T11e
result of the study has a great signification not only fOr ATM but also fOr other field using high
speed switcll.
Tlle goaI of this article is to design a high speed ATM switch system, so there are three pars
of tllis articIe.
l) Most switcll systems used now are studied. The result of the research of most switcl1
system including Time Divided Switch systeln and Space Divided Switch system, and its buffer
strategy indicate that Tilne Divided Switch system can not meet with the data transfer speed in
fabric when design large scale high speed switch system because of the process of semiconductor.
So Space Divided Switch systeln is chosen in our design.
2) Clloose the space divided switcl1 fabrics and their scheduling algorithm for l1igh speed
switch systel11 based on analysis and stimulation. The perfonnances of two main space divided
switch fabrics including Crossbar and Multistage Intercon11ect Network (MIN), including Extend
MuItistage I11terconnect Network (EMlN) are study careful1y. The result of ana1ysis a11d
stilllulation of buftbr strategy including input buffer and output buffer explain why using input
buffer. Because of block in head of line (HOL), input buffer strategy make the whole switch
system perfOrmances declining drastically at heavy oflbred load, and some improvements of input
buffer strategy are put fOrward to overcoming tlle head of line block. Virtual output queues (VOQ)
is chosen as input buffer Strategy. DPA and iLQF ce1l scheduling algorithms fOr VOQ are
silllulated. The rueslt of simulatiol1 is tl1e base of hardware design.
3) Design switch system using EDA based on the result of a11alysis. Because the function of
switch system is very complicated, some modules are designed by schematics directly, most
modules are designed by Verilog HDL using EDA technology, synthesized by the Synopsys
software. At last a high speed ATM switch system is designed, including VOQ as input buffer
strategy DPA cell scheduling algorithm and Crossbar switch fabric.
本论文的目的是设计一个高速ATM交换系统，主要分成3个部分：
1)对目前交换系统进行分析研究。本论文定性分析了目前的分析交换系统，主要是时分交换系统和空分交换系统，以及空分交换结构对应缓存策略。由于目前光通讯技术的发展速度超过半导体工艺的进展速度，时分交换技术的分析结果表明它已经无法满足高速大规模交换系统的要求。
2)确定高速交换系统所采用的交换结构，对其进行详细的分析仿真。本论文将定量的分析和仿真空分交换结构和对应的调度算法，深入的了解Crossbar利MIN(包括EMIN)空分交换系统各方面的性能，分析利仿真输入缓存和输出缓存的缓存策略。由于输入缓存的队头阻塞使得高负载条件下输入缓存策略的交换系统各方面性能急剧下降，由此提出了克服输入缓存队头阻塞的改进方法，最后本文决定选用虚拟输出队列(VOQ)的输入缓存策略，并且研究了与虚拟输出队列相对应的iLQF(最长队列优先)和DPA(对角线优先)信元调度算法，为交换系统的ASIC设计提供依据。
3)根据前面的结论，设计出交换系统。在前面分析的基础上根据目前的条件，对一个空分交换系统各模块进行前端设计和仿真，由于交换系统的功能复杂，我们一部分将采用直接画原理图的方法进行设计，大部分将采用集成电路设计自动化的方法进行设计，即采用硬件设计语言Verilog—HDL进行设计，用Synopsys软件对设计进行综合，生成线路图，然后作门级电路仿真。在完成各模块的设计后，我们设计一个完整的ATM交换系统，输入模块采用虚拟输出队列的缓存策略，调度算法用对角线优先的DPA凋度算法，采用Crossbar的交换结构，然后对其进行仿真和计算，结果表明我们设计交换系统与目前光纤通讯网络的数据传输速度匹配。
ln these years the quick develop1nent of fabric com1nunication technology make the switch
systeln becoIni11g tI1e barrier of lnodern high speed communication network. So study, design and
lllanulhcture high speed switch system are very important fOr modern high speed communication
network. Asynchronous transfer mode (A1M) had been specified as the base of the broadband
integrated services digita1 network by international telecommunication union telecommunication
standardization sector (lTU-T). One important method of ATM to realize high speed data transfer
is using cell whose size is tixed. Because of it, ASlC cat1 deal with cell directIy. So ATM switch
cal1 switcl1 ceII at high speed, and study on A1'M switch is of great empl1asis in these years. T11e
result of the study has a great signification not only fOr ATM but also fOr other field using high
speed switcll.
Tlle goaI of this article is to design a high speed ATM switch system, so there are three pars
of tllis articIe.
l) Most switcll systems used now are studied. The result of the research of most switcl1
system including Time Divided Switch systeln and Space Divided Switch system, and its buffer
strategy indicate that Tilne Divided Switch system can not meet with the data transfer speed in
fabric when design large scale high speed switch system because of the process of semiconductor.
So Space Divided Switch systeln is chosen in our design.
2) Clloose the space divided switcl1 fabrics and their scheduling algorithm for l1igh speed
switch systel11 based on analysis and stimulation. The perfonnances of two main space divided
switch fabrics including Crossbar and Multistage Intercon11ect Network (MIN), including Extend
MuItistage I11terconnect Network (EMlN) are study careful1y. The result of ana1ysis a11d
stilllulation of buftbr strategy including input buffer and output buffer explain why using input
buffer. Because of block in head of line (HOL), input buffer strategy make the whole switch
system perfOrmances declining drastically at heavy oflbred load, and some improvements of input
buffer strategy are put fOrward to overcoming tlle head of line block. Virtual output queues (VOQ)
is chosen as input buffer Strategy. DPA and iLQF ce1l scheduling algorithms fOr VOQ are
silllulated. The rueslt of simulatiol1 is tl1e base of hardware design.
3) Design switch system using EDA based on the result of a11alysis. Because the function of
switch system is very complicated, some modules are designed by schematics directly, most
modules are designed by Verilog HDL using EDA technology, synthesized by the Synopsys
software. At last a high speed ATM switch system is designed, including VOQ as input buffer
strategy DPA cell scheduling algorithm and Crossbar switch fabric.
引文
[1] William Stallings著 程时端 隆克平 祝东海等译《ISDN、B-ISDN与帧中继和ATM》机械工业出版社 2001年9月
[2] Kenneth J. Schultz, P. Glenn Gulak, "Physical Performance Limits for Shared Buffer ATM Switches" IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 45, NO.8, AUGUST 1997
[3] M．R．Karim著韩毅刚译《ATM技术实用教程》 电子工业出版社2000年8月
[4] Mischa Schwartz《宽带网络性能分析》清华大学出版社1998年4月
[5] C.Wu and T. Feng "On a class of multistage interconnection networks" IEEE Transaction on Computer VOL 29 pp694-702 Aug 1980
[6] 陈锡生 《ATM交换技术》 人民邮电出版社2000年4月
[7] William Stallings著 齐望东等译 《高速网络-TCP／IP和ATM的设计原理》 电子工业出版社1999年
[8] 陈鑫林编著 《现代通信中的排队论》 电子工业出版社 1999年11月
[9] 郭东辉 李立峰等“ATM交换智能控制器的VHDL兑现方案”《1999年中国神经网络与信号处理学术会议论文集》电子工业出版社1999年11月
[10] 李立峰 郭东辉等“神经网络在信元交换控制中的应用”《1999年中国神经网络与信号处理学术会议论文集》电子工业出版社1999年11月
[11] 川岛幸之助 町原文明等《通信流理论基础与多媒体通信网》清华大学出版社2000年11月
[12] Inge Svinnset "Nonblocking ATM Switch Networks" IEEE Transactions on Communications VOL 42. NO.2/3/4 1994
[13] Takeo Koinuma Noriham Miyaho "ATM in B-ISDN Communication Systems and VLSI Realization" IEEE Journal of Solid-State Circuits VOL 30 NO.4 APRIL 1995
[14] Youn Chan Jung and Chong-Kwan Un "Banyan Multipath Self_Routing ATM Switches with Shared Buffer Type Switch Elements" IEEE Transactions on Communications VOL 43 NO 11 November 1995
[14] Kwan L. Yeuog and Shi Hai "Throughput analysis for input-buffered ATM switches with multiple FIFO queues per input port" Electronics Letters 11th September 1997 VOL33 No19
[15] Naoaki Yamanaka, "Breakthrough Technologies for the High-Performance Electrical ATM Switching System" JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL.16, NO.12,DECEMBER 1998
[16] Donpaul C. Stephens, Jon C. R. Bennett, Hui Zhang, "Implementing Scheduling Algorithms in High-Speed Networks" IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL.17, NO.6, JUNE 1999
[17] Jae-Hyun Park, Hyunsoo Yoon, Heung-Kyu Lee "The Deflection Self-Routing Banyan Network: A Large-Scale ATM Switch Using the Fully Adaptive Self-Routing and its Performance Analyses" IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 7, NO. 4, AUGUST 1999
[18] Nick McKeown, "The iSLIP Scheduling Algorithm for Input-Queued Switches"IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 7, NO.2, APRIL 1999
[19] 李立峰 《宽带通讯交换的信元智能调度及性能分析研究》厦门大学博士学位论文2000年9月
[20] Kohei Shiomoto, Masanori Uga, Masaaki Omotani, Shigeki Shimizu, and Takeshi Chimaru "Scalable Multi-QoS IP+ATM Switch Router Architecture" IEEE Communications Magazine December 2000
[21] S.Keshav and Rosen Sharma "Issues and Trends in Router Design" IEEE Communications Magazine May 1998
[22] A.Santhanam A.Karandikar "Window-based cell scheduling algorithm for VLSI implementation of an input-queued ATM switch" IEE Proc-Commun Vol 147 No2 April 2000
[2] Kenneth J. Schultz, P. Glenn Gulak, "Physical Performance Limits for Shared Buffer ATM Switches" IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 45, NO.8, AUGUST 1997
[3] M．R．Karim著韩毅刚译《ATM技术实用教程》 电子工业出版社2000年8月
[4] Mischa Schwartz《宽带网络性能分析》清华大学出版社1998年4月
[5] C.Wu and T. Feng "On a class of multistage interconnection networks" IEEE Transaction on Computer VOL 29 pp694-702 Aug 1980
[6] 陈锡生 《ATM交换技术》 人民邮电出版社2000年4月
[7] William Stallings著 齐望东等译 《高速网络-TCP／IP和ATM的设计原理》 电子工业出版社1999年
[8] 陈鑫林编著 《现代通信中的排队论》 电子工业出版社 1999年11月
[9] 郭东辉 李立峰等“ATM交换智能控制器的VHDL兑现方案”《1999年中国神经网络与信号处理学术会议论文集》电子工业出版社1999年11月
[10] 李立峰 郭东辉等“神经网络在信元交换控制中的应用”《1999年中国神经网络与信号处理学术会议论文集》电子工业出版社1999年11月
[11] 川岛幸之助 町原文明等《通信流理论基础与多媒体通信网》清华大学出版社2000年11月
[12] Inge Svinnset "Nonblocking ATM Switch Networks" IEEE Transactions on Communications VOL 42. NO.2/3/4 1994
[13] Takeo Koinuma Noriham Miyaho "ATM in B-ISDN Communication Systems and VLSI Realization" IEEE Journal of Solid-State Circuits VOL 30 NO.4 APRIL 1995
[14] Youn Chan Jung and Chong-Kwan Un "Banyan Multipath Self_Routing ATM Switches with Shared Buffer Type Switch Elements" IEEE Transactions on Communications VOL 43 NO 11 November 1995
[14] Kwan L. Yeuog and Shi Hai "Throughput analysis for input-buffered ATM switches with multiple FIFO queues per input port" Electronics Letters 11th September 1997 VOL33 No19
[15] Naoaki Yamanaka, "Breakthrough Technologies for the High-Performance Electrical ATM Switching System" JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL.16, NO.12,DECEMBER 1998
[16] Donpaul C. Stephens, Jon C. R. Bennett, Hui Zhang, "Implementing Scheduling Algorithms in High-Speed Networks" IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL.17, NO.6, JUNE 1999
[17] Jae-Hyun Park, Hyunsoo Yoon, Heung-Kyu Lee "The Deflection Self-Routing Banyan Network: A Large-Scale ATM Switch Using the Fully Adaptive Self-Routing and its Performance Analyses" IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 7, NO. 4, AUGUST 1999
[18] Nick McKeown, "The iSLIP Scheduling Algorithm for Input-Queued Switches"IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 7, NO.2, APRIL 1999
[19] 李立峰 《宽带通讯交换的信元智能调度及性能分析研究》厦门大学博士学位论文2000年9月
[20] Kohei Shiomoto, Masanori Uga, Masaaki Omotani, Shigeki Shimizu, and Takeshi Chimaru "Scalable Multi-QoS IP+ATM Switch Router Architecture" IEEE Communications Magazine December 2000
[21] S.Keshav and Rosen Sharma "Issues and Trends in Router Design" IEEE Communications Magazine May 1998
[22] A.Santhanam A.Karandikar "Window-based cell scheduling algorithm for VLSI implementation of an input-queued ATM switch" IEE Proc-Commun Vol 147 No2 April 2000