锁相环SET效应敏感性分析与设计加固
摘要
随着工艺特征尺寸的不断缩小,单粒子效应日趋主导集成电路的辐射效应。作为高性能芯片的关键部件,锁相环(PLL)容易受到单粒子瞬变(Single-Event Transient,SET)效应的影响,进而对芯片的时钟产生巨大的影响。因此对辐射加固锁相环的研究得到了广泛的关注,成为当今抗辐射集成电路研究的热点问题之一。
PLL电路结构较复杂,其SET作用机理和诸多因素有关,对其SET效应的量化分析一直是PLL单粒子瞬态效应研究的重点与难点。本文从量化分析的角度对PLL的SET效应进行了研究和电路加固,主要工作和创新点有以下几个方面:
1、首次提出并实现了SET效应敏感性分析自动化平台,用以对电路的SET效应进行全面的量化分析。该平台支持多元组条件下的SET大规模电路模拟的自动化过程;直接基于SPICE电路网表,提取了待轰击节点的位置信息;在此基础上实现了Hspice电路模拟脚本的自动生成;提供了配置接口,可以灵活地根据需要产生进行模拟的Hspice脚本;提供了高效清晰的目录和数据管理机制,并解决了大规模模拟中的数据存储问题。
2、提出了有效的SET效应量化分析指标,对一款基于180nm CMOS工艺的1GHz PLL电路进行了全面的量化分析。结果表明,采用TSPC触发器结构的分频器是整体上最敏感的模块,而电荷泵受到SET影响后对VCO(压控振荡器)的控制电压影响最大,同时VCO中的偏置电路也是敏感点。相较而言,采用了RS触发器结构的鉴频鉴相器对SET的抵抗能力较强。
3、采用Verilog-A模型对敏感性分析过程进行了优化。实验结果表明,基于Verilog-A的混合模拟技术极大地加速了模拟过程,同时保持了电路对SET效应敏感性的区分度;而基于Verilog-A的电压耦合模型则创造性地将Verilog-A建模与查找表(LUT)技术结合到一起,成功地将LUT技术应用到设计流程中来,不仅改善了SET模型的精度,而且能够和现有的设计流程良好地兼容。
4、对PLL电路进行了加固设计并量化地评估了加固效果。基于分析结果,采用RHBD(Radiation Hardened By Design)设计方法学,加固了PLL电路,投片并开展了电路功能测试。结果表明,该芯片能够稳定地输出400MHz—1360MHz的时钟信号。量化分析表明,加固后的锁相环无论是锁相环的最坏情况还是整个PLL的SET敏感性均得到了有效的改善,各个电路模块也获得了良好的加固效果。
With the continual decreasing of the feature size, single event effects is dominating the radiation effects of IC. Single event transients can dramatically affect the Phase Locked Loops (PLLs), which act as the key components of high performance chips. This impact will further disturb the clock network of the whole chip. Thus, it has gained extensive attention on the hardening technique of PLL circuits.
It has been an important, however difficult, issue to quantitatively analyze the SETs in PLLs, for the circuit complexity and varied factors affecting the phenomenon. This paper uses a quantitative view to research and harden the PLL circuits, including works and innovations as below:
1. For the first time ever, an automatic SET analysis platform is designed and implemented to get a full understanding of the SET responses by means of large scale of Hspice simulations. The platform has the features of circuit topology extraction directly from SPICE netlist, simulation scripts automatic generation and flexible mechanism to configure the tool. Besides, the platform takes good advantage of directory and files management, and conquered the“memory wall”barrier in large scale simulation and data processing.
2. The paper puts forward effective metrics to guideline the analyses, and a 1GHz PLL designed in 180nm standard CMOS process is fully evaluated by the sensitivity analysis platform. Results indicate that the TSPC based frequency divider is the most sensitive module of the PLL, and the charge pump may exert the greatest impact on the control voltage of the VCO. Meanwhile the bias circuit of the VCO is also the fragile parts of the PLL. However, the PFD, which is implemented in RS flip-flop, has good strength against SET.
3. Verilog-A based technique is adopted to optimize the sensitivity analyses. Experiments indicate that the Verilog-A based mixed-level simulation gets a well speed up while maintaining the original distinction of SET sensitivity. As for the Verilog-A based LUT model, it goes well with the current design flow and improves the SET precision in SPICE.
4. The PLL circuits are hardened against SETs and evaluated by the analysis platform. On the solid basis of the evaluation conclusions, a radiation hardened PLL is designed and taped out in RHBD methodology. Electrical tests manifest that it can work well with output frequency spans from 400MHz to 1360MHz. The evaluation results indicate that the PLL has been effectively improved in either the worst case or the overall SET sensitivity. Moreover, each module is checked to work better under SETs.
PLL电路结构较复杂,其SET作用机理和诸多因素有关,对其SET效应的量化分析一直是PLL单粒子瞬态效应研究的重点与难点。本文从量化分析的角度对PLL的SET效应进行了研究和电路加固,主要工作和创新点有以下几个方面:
1、首次提出并实现了SET效应敏感性分析自动化平台,用以对电路的SET效应进行全面的量化分析。该平台支持多元组条件下的SET大规模电路模拟的自动化过程;直接基于SPICE电路网表,提取了待轰击节点的位置信息;在此基础上实现了Hspice电路模拟脚本的自动生成;提供了配置接口,可以灵活地根据需要产生进行模拟的Hspice脚本;提供了高效清晰的目录和数据管理机制,并解决了大规模模拟中的数据存储问题。
2、提出了有效的SET效应量化分析指标,对一款基于180nm CMOS工艺的1GHz PLL电路进行了全面的量化分析。结果表明,采用TSPC触发器结构的分频器是整体上最敏感的模块,而电荷泵受到SET影响后对VCO(压控振荡器)的控制电压影响最大,同时VCO中的偏置电路也是敏感点。相较而言,采用了RS触发器结构的鉴频鉴相器对SET的抵抗能力较强。
3、采用Verilog-A模型对敏感性分析过程进行了优化。实验结果表明,基于Verilog-A的混合模拟技术极大地加速了模拟过程,同时保持了电路对SET效应敏感性的区分度;而基于Verilog-A的电压耦合模型则创造性地将Verilog-A建模与查找表(LUT)技术结合到一起,成功地将LUT技术应用到设计流程中来,不仅改善了SET模型的精度,而且能够和现有的设计流程良好地兼容。
4、对PLL电路进行了加固设计并量化地评估了加固效果。基于分析结果,采用RHBD(Radiation Hardened By Design)设计方法学,加固了PLL电路,投片并开展了电路功能测试。结果表明,该芯片能够稳定地输出400MHz—1360MHz的时钟信号。量化分析表明,加固后的锁相环无论是锁相环的最坏情况还是整个PLL的SET敏感性均得到了有效的改善,各个电路模块也获得了良好的加固效果。
With the continual decreasing of the feature size, single event effects is dominating the radiation effects of IC. Single event transients can dramatically affect the Phase Locked Loops (PLLs), which act as the key components of high performance chips. This impact will further disturb the clock network of the whole chip. Thus, it has gained extensive attention on the hardening technique of PLL circuits.
It has been an important, however difficult, issue to quantitatively analyze the SETs in PLLs, for the circuit complexity and varied factors affecting the phenomenon. This paper uses a quantitative view to research and harden the PLL circuits, including works and innovations as below:
1. For the first time ever, an automatic SET analysis platform is designed and implemented to get a full understanding of the SET responses by means of large scale of Hspice simulations. The platform has the features of circuit topology extraction directly from SPICE netlist, simulation scripts automatic generation and flexible mechanism to configure the tool. Besides, the platform takes good advantage of directory and files management, and conquered the“memory wall”barrier in large scale simulation and data processing.
2. The paper puts forward effective metrics to guideline the analyses, and a 1GHz PLL designed in 180nm standard CMOS process is fully evaluated by the sensitivity analysis platform. Results indicate that the TSPC based frequency divider is the most sensitive module of the PLL, and the charge pump may exert the greatest impact on the control voltage of the VCO. Meanwhile the bias circuit of the VCO is also the fragile parts of the PLL. However, the PFD, which is implemented in RS flip-flop, has good strength against SET.
3. Verilog-A based technique is adopted to optimize the sensitivity analyses. Experiments indicate that the Verilog-A based mixed-level simulation gets a well speed up while maintaining the original distinction of SET sensitivity. As for the Verilog-A based LUT model, it goes well with the current design flow and improves the SET precision in SPICE.
4. The PLL circuits are hardened against SETs and evaluated by the analysis platform. On the solid basis of the evaluation conclusions, a radiation hardened PLL is designed and taped out in RHBD methodology. Electrical tests manifest that it can work well with output frequency spans from 400MHz to 1360MHz. The evaluation results indicate that the PLL has been effectively improved in either the worst case or the overall SET sensitivity. Moreover, each module is checked to work better under SETs.
引文
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