提高IC测试并行度及其程序优化的研究
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摘要
半导体测试是半导体产业链中不可或缺的一环,它贯穿于从芯片设计到大规模生产的全过程。随着对芯片测试的重视度的提高,测试成本所占比重越来越大。为了达到节约成本的目的,提出了测试并行度的概念,即同时测试多颗物料。
首先基于泰瑞达J750测试平台,阐述自动测试机的原理,并分析了SOC测试原理及其方法。为了能够达到测试并行度的增加,需要进行测试平台的升级。
其次,重点阐述了测试并行度转换的方法,并进行了测试软件和硬件电路改善。为了能够一次测试多颗物料,研发了一种新的测试同步的方法。其中详细介绍了测试真值表,以及如何利用VB达到测试同步的目的。两种改善方法相互配合,达到了测试程序的改善。使得测试机从原来的一次测一颗芯片增加到现在的一次测八颗芯片的目的,并行度得到明显改善,这是此工程改善项目的重点和难点。
再次,重新进行了测试转接板的设计。阐述了测试板设计中注意事项及细节,及其对测试稳定性的影响,即如何避免测试中的热切换,布线的规则等等。
最后,介绍了优化测试程序的几种方法,电子身份证在测试中的应用和优点,以及应用统计学和六西格马的方法进行分析等。
通过并行度转换提高了生产效率,节约了测试成本;通过测试转接板硬件的重新设计,提高了硬件的使用寿命和测试的稳定性;通过测试程序的优化,提高了测试良品率,降低了复测率。总之,通过这些改善项目,生产效率明显提高,测试成本显著降低。最终实现半导体测试的优化。
Semiconductor test is indispensable process in the semiconductor industry, it run through all processes from IC design to production roll in. Because test cost take more and more proportion in whole cost, in order to save cost, we put forward test parallelism concept. So test many devices at one time. This thesis introduce how to complete test parallelism improve project.
At first, briefly state automatic test equipment principle per Teradyne J750 tester. Analyze test theory and method about some modules of SOC (System on chip). Should upgrade test system in order to complete test parallelism improvement.
After that, this thesis introduces the parallelism methods, including software and hardware improvement. We researched and improved new match method in order to test many devices at one time by Teradyne help. It recommends test pattern, and how to archive test match purpose using VBT code. Complete test program improvement after two methods mutual cooperation. Make tester test device improve from one to eight once a time. This is the important and difficult points in this project improvement.
In the next place, redesign new load board. Introduce load board design detail and attentions which impact on test robust performance. For example: how to forbid hot switch, how to select relay, load board layout and wire arrange principle, and so on.
Finally, this thesis introduces how to optimize test program, ECID (Electrical Identity) application and advantage at test process, and the methods to analyze test issues and matters by using statistical and six sigma methods, and so on.
Efficiency is enhanced and the costs are saved by parallelism improvement;hardware can be used for a longer time and test stability is increased by load board re-design;1st pass yield has been raised and the rest rate has been reduced by optimizing test program. To sum up, produce efficiency is enhanced, cost reduction is strikingly by these improvements and eventually optimization of the semiconductor test has been achieved.
首先基于泰瑞达J750测试平台,阐述自动测试机的原理,并分析了SOC测试原理及其方法。为了能够达到测试并行度的增加,需要进行测试平台的升级。
其次,重点阐述了测试并行度转换的方法,并进行了测试软件和硬件电路改善。为了能够一次测试多颗物料,研发了一种新的测试同步的方法。其中详细介绍了测试真值表,以及如何利用VB达到测试同步的目的。两种改善方法相互配合,达到了测试程序的改善。使得测试机从原来的一次测一颗芯片增加到现在的一次测八颗芯片的目的,并行度得到明显改善,这是此工程改善项目的重点和难点。
再次,重新进行了测试转接板的设计。阐述了测试板设计中注意事项及细节,及其对测试稳定性的影响,即如何避免测试中的热切换,布线的规则等等。
最后,介绍了优化测试程序的几种方法,电子身份证在测试中的应用和优点,以及应用统计学和六西格马的方法进行分析等。
通过并行度转换提高了生产效率,节约了测试成本;通过测试转接板硬件的重新设计,提高了硬件的使用寿命和测试的稳定性;通过测试程序的优化,提高了测试良品率,降低了复测率。总之,通过这些改善项目,生产效率明显提高,测试成本显著降低。最终实现半导体测试的优化。
Semiconductor test is indispensable process in the semiconductor industry, it run through all processes from IC design to production roll in. Because test cost take more and more proportion in whole cost, in order to save cost, we put forward test parallelism concept. So test many devices at one time. This thesis introduce how to complete test parallelism improve project.
At first, briefly state automatic test equipment principle per Teradyne J750 tester. Analyze test theory and method about some modules of SOC (System on chip). Should upgrade test system in order to complete test parallelism improvement.
After that, this thesis introduces the parallelism methods, including software and hardware improvement. We researched and improved new match method in order to test many devices at one time by Teradyne help. It recommends test pattern, and how to archive test match purpose using VBT code. Complete test program improvement after two methods mutual cooperation. Make tester test device improve from one to eight once a time. This is the important and difficult points in this project improvement.
In the next place, redesign new load board. Introduce load board design detail and attentions which impact on test robust performance. For example: how to forbid hot switch, how to select relay, load board layout and wire arrange principle, and so on.
Finally, this thesis introduces how to optimize test program, ECID (Electrical Identity) application and advantage at test process, and the methods to analyze test issues and matters by using statistical and six sigma methods, and so on.
Efficiency is enhanced and the costs are saved by parallelism improvement;hardware can be used for a longer time and test stability is increased by load board re-design;1st pass yield has been raised and the rest rate has been reduced by optimizing test program. To sum up, produce efficiency is enhanced, cost reduction is strikingly by these improvements and eventually optimization of the semiconductor test has been achieved.
引文
[1] (美)Rochit Rajsuman, System-on-a-Chip: Design and Test,北京航空航天大学出版社,2003.118~136
[2]常越,MC68HC08单片机原理及C语言开发实例,北京航空航天大学出版社,2005.122~136
[3]张友德等,68HC08系列单片机原理与应用,复旦大学出版社,2001。149~155,218~238
[4] Guy Perry,The Fundamentals of Digital S电磁辐射conductor Testing,Soft Test Inc,1996,46~158。
[5] Teradyne J750 User Guide,Teradyne Co. Ltd. USA. 2008. All
[6]王守三等,PCB的电磁兼容设计技术、技巧和工艺,机械工业出版社,2008. 26~68,156~200
[7]李平等,集成电路设计与制造,电子科技大学微电子与固体电子学院,2001. 56~234
[8] ECT测试转接板(Load Board)内部培训资料,2006. All
[9] Michael Quirk etc,半导体制造技术,电子工业出版社,2004. 26~200
[10]张丽华,单片开关电源—应用电路·电磁兼容·PCB布线,高等教育出版社,2003. 122~200
[11]张睿,ALTIUM DESIGNER 6.0原理图与PCB设计,电子工业出版社,2007. 50~100
[12]Freescale, MC68HC908GR16A data book, Freescale, 2006. 50~200
[13]Freescale, Burn In User Manual, Freescale, 2005.50~200
[14]陈佳丽,Visual Basic程序设计基础与实训教程,清华大学出版社,2006. 68~300
[15]潘曙娟等,基于自动测试机的IC测试原理、方法及故障分析,半导体学报,2006-12.第27卷增刊
[16]坂口英明等,半导体测试装置和半导体测试方法,夏普株式会社,2002-07
[17]岸上真也,半导体集成电路及其测试方法,夏普株式会社, 2005-11-18
[18]陈凯,基于嵌入式核测试复用的数字SOC测试技术研究,桂林电子科技大学,2007-3 [19]泰瑞达推出超大规模集成测试系统INTEGRA J750—半导体测试技术的突破,迪艾电脑有限公司,电子测试期刊1998- 07期。
[20]孙以材,半导体测试技术,北京冶金工业出版社,2005. 56~88
[21]刘新福等,半导体测试技术原理与应用,冶金工业出版社,2007 -1. 52~68
[2]常越,MC68HC08单片机原理及C语言开发实例,北京航空航天大学出版社,2005.122~136
[3]张友德等,68HC08系列单片机原理与应用,复旦大学出版社,2001。149~155,218~238
[4] Guy Perry,The Fundamentals of Digital S电磁辐射conductor Testing,Soft Test Inc,1996,46~158。
[5] Teradyne J750 User Guide,Teradyne Co. Ltd. USA. 2008. All
[6]王守三等,PCB的电磁兼容设计技术、技巧和工艺,机械工业出版社,2008. 26~68,156~200
[7]李平等,集成电路设计与制造,电子科技大学微电子与固体电子学院,2001. 56~234
[8] ECT测试转接板(Load Board)内部培训资料,2006. All
[9] Michael Quirk etc,半导体制造技术,电子工业出版社,2004. 26~200
[10]张丽华,单片开关电源—应用电路·电磁兼容·PCB布线,高等教育出版社,2003. 122~200
[11]张睿,ALTIUM DESIGNER 6.0原理图与PCB设计,电子工业出版社,2007. 50~100
[12]Freescale, MC68HC908GR16A data book, Freescale, 2006. 50~200
[13]Freescale, Burn In User Manual, Freescale, 2005.50~200
[14]陈佳丽,Visual Basic程序设计基础与实训教程,清华大学出版社,2006. 68~300
[15]潘曙娟等,基于自动测试机的IC测试原理、方法及故障分析,半导体学报,2006-12.第27卷增刊
[16]坂口英明等,半导体测试装置和半导体测试方法,夏普株式会社,2002-07
[17]岸上真也,半导体集成电路及其测试方法,夏普株式会社, 2005-11-18
[18]陈凯,基于嵌入式核测试复用的数字SOC测试技术研究,桂林电子科技大学,2007-3 [19]泰瑞达推出超大规模集成测试系统INTEGRA J750—半导体测试技术的突破,迪艾电脑有限公司,电子测试期刊1998- 07期。
[20]孙以材,半导体测试技术,北京冶金工业出版社,2005. 56~88
[21]刘新福等,半导体测试技术原理与应用,冶金工业出版社,2007 -1. 52~68
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