以低成本测试机实现含高速接口电路芯片测试技术
摘要
随视频设备、个人电脑、宽带接入技术的迅速发展,进而在设备中进行3D处理、视频交换以及复杂的运算等功能导致数据的传输和处理量急剧增大。为了满足这些数据在处理器、存储和外围设备之间以及网络设备之间高速交换的需要,出现了多种高速接口,如USB、SATA、XAUI、DDR等。如今这些高速接口标准的传输速度已经达到Gbps量级,如DDR3接口速度达1.6Gbps、SATA2.0接口速度达到3Gbps, SATA3.0甚至将达到6Gbps。
对于高速接口芯片,传统的测试方法是采用具有与被测芯片最高速率相同或更高速率的测试机,来实现对高速接口的功能和参数测试。对于含有Gbps量级高速接口的芯片,这将对测试机提出极高的要求；相应来说,测试成本也会相应大幅提高。目前市场上可以满足Gbps量级高速信号测试的自动测试机(ATE)如泰瑞达的Flex、UltraFlex、惠瑞杰的Pinscale93000RF等生产测试成本都很高,一般在150美元每小时以上。但对于一款复杂的SoC芯片,除了高速接口需要非常高的测试速率外,大部分测试项实际上并不需要特别高的测试速率；而且运行实现高速接口测试的复杂代码本生也会占用较多的测试时间,从而增加产品的测试成本,影响产品的竞争力。因此,如何在不使用昂贵的高速ATE条件下,低成本地实现含有高速电路接口的芯片量产测试,是一个值得研究的课题。
本论文将一款含有传输速度可达3Gbps的XAUI接口芯片作为研究的对象,研究基于低成本(低速率)测试机平台和特定可测试性设计(DFT)电路,以环回方式实现了高速接口的功能测试及直流参数测试,从而达到大幅降低该集成芯片测试成本的目地。通过本课题的研究表明该测试方案是一种经济、有效的高速接口电路芯片测试方案,具有现实的参考价值。
Recently video devices, personal computers and broadband access technology are fast developing. At the same time,3D processing, video exchanging and complicated computation work lead to quick expanding of the data. In order to satisfy the constantly increasing requirement of big volume data exchanging work among processor, memory, peripheral devices and network devices, more and more high speed interfaces, such as DDR, USB, SATA and XAUI are introduced. Nowadays speed unit for these high speed interfaces is Gbps and the popular DDR3 interface has a speed of 1.6Gbps, SATA2 can reach 3Gbps. The new interface such as SATA3.0 has a speed of 6Gbps.
The traditional method used to test high interface needs to implement high performance tester which has the same or higher speed as DUT in order to do function test and parameter test of the interface. Adapting this test methodology requires advanced capability of Automatic Test Tester (ATE), thus push up the test cost. The popular ATEs which can satisfy Gbps speed testing requirement are Teradyne Flex, UltraFlex and Verigy Pinscale93000RF. But cost of these ATE is pretty high, which can reach 150 USD/h. For a complicated SoC chip, only the high speed interface needs very high test speed while the other parts can be tested at low speed. These complicated test code will also occupy a lot of the tester time, add more test cost and low the competitiveness of product. Thus, it is a worthwhile task for tester engineers and designers that testing chip with high speed interface without using high speed ATE.
Thesis chooses a chip with 3Gpbs XAUI interface as a study target. With the help of specific DTF(Design for Test) circuit, finally complete mass production test program which achieves the function and DC parameter of the high speed interface on low speed and low cost ATE. Studying of this thesis verified that this test mythology is economical and efficient method for high speed interface testing.
对于高速接口芯片,传统的测试方法是采用具有与被测芯片最高速率相同或更高速率的测试机,来实现对高速接口的功能和参数测试。对于含有Gbps量级高速接口的芯片,这将对测试机提出极高的要求；相应来说,测试成本也会相应大幅提高。目前市场上可以满足Gbps量级高速信号测试的自动测试机(ATE)如泰瑞达的Flex、UltraFlex、惠瑞杰的Pinscale93000RF等生产测试成本都很高,一般在150美元每小时以上。但对于一款复杂的SoC芯片,除了高速接口需要非常高的测试速率外,大部分测试项实际上并不需要特别高的测试速率；而且运行实现高速接口测试的复杂代码本生也会占用较多的测试时间,从而增加产品的测试成本,影响产品的竞争力。因此,如何在不使用昂贵的高速ATE条件下,低成本地实现含有高速电路接口的芯片量产测试,是一个值得研究的课题。
本论文将一款含有传输速度可达3Gbps的XAUI接口芯片作为研究的对象,研究基于低成本(低速率)测试机平台和特定可测试性设计(DFT)电路,以环回方式实现了高速接口的功能测试及直流参数测试,从而达到大幅降低该集成芯片测试成本的目地。通过本课题的研究表明该测试方案是一种经济、有效的高速接口电路芯片测试方案,具有现实的参考价值。
Recently video devices, personal computers and broadband access technology are fast developing. At the same time,3D processing, video exchanging and complicated computation work lead to quick expanding of the data. In order to satisfy the constantly increasing requirement of big volume data exchanging work among processor, memory, peripheral devices and network devices, more and more high speed interfaces, such as DDR, USB, SATA and XAUI are introduced. Nowadays speed unit for these high speed interfaces is Gbps and the popular DDR3 interface has a speed of 1.6Gbps, SATA2 can reach 3Gbps. The new interface such as SATA3.0 has a speed of 6Gbps.
The traditional method used to test high interface needs to implement high performance tester which has the same or higher speed as DUT in order to do function test and parameter test of the interface. Adapting this test methodology requires advanced capability of Automatic Test Tester (ATE), thus push up the test cost. The popular ATEs which can satisfy Gbps speed testing requirement are Teradyne Flex, UltraFlex and Verigy Pinscale93000RF. But cost of these ATE is pretty high, which can reach 150 USD/h. For a complicated SoC chip, only the high speed interface needs very high test speed while the other parts can be tested at low speed. These complicated test code will also occupy a lot of the tester time, add more test cost and low the competitiveness of product. Thus, it is a worthwhile task for tester engineers and designers that testing chip with high speed interface without using high speed ATE.
Thesis chooses a chip with 3Gpbs XAUI interface as a study target. With the help of specific DTF(Design for Test) circuit, finally complete mass production test program which achieves the function and DC parameter of the high speed interface on low speed and low cost ATE. Studying of this thesis verified that this test mythology is economical and efficient method for high speed interface testing.
引文
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[2].汪荣源.电路理论基础[M]浙江大学出版社1997.5
[3].于歆杰(译者).模拟电路[M]清华大学出版社2008
[4].毕岗.电磁场与微波[M]浙江大学出版社2006
[5].黄智伟.印制电路板(PCB)设计技术与实践[M].2009
[6]. Philippe Cauvet. Advanced High Speed I/O Test Cookbook[M].2005
[7]. Maxim.Inc. Introduction to LVDS, PECL, and CML[EB].2008
[8]. Verigy.Inc. Verigy93000 SOC Series User Training[EB].2000
[9]. Verigy.Inc. System Reference[EB].2010
[10]. Verigy.Inc.Test Method Reference[EB] 2010
[11]. Verigy.Inc. Multi-Sites Reference[EB] 2010
[12]. Justin Redd.A second look at jitter:calculating bit error rates[EB]. http://www.commSdesign.com/story/OEG20020306S0023.2001
[13].泰克中国有限公司深入剖析眼图及高速串行设计中的眼图测试[J].国外电子测量技术2011(4)
[14].杨俊峰,高速数字串行通信中的时间抖动研究[D],中国科学技术大学,2005
[15]. Trident.Inc. Moca Chip Datasheet[EB].2011
[16]. Hubert Werkmann, Verigy X-Mode Pattern Synchronization to Free Running Bit Streams[EB] 2006
[17]. IEEE.Clause 47. XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI). IEEE Std 802.3-2008 Section 4. Institute of Electrical and Electronics Engineers[S].2008
[18]. J.M.Martins Ferreira. DESIGN FOR TEST STANDARDS[M].2000
[19]. IEEE.IEEE Std 1149.1-2001[S].2001
[20]. Michael L Bushnell and Vishwani D. Agrawal. Essentials of Electronic Testing for Digital, memory & Mixed-Signal VLSI Circuits[M]. Kluwer Academic Publishers.2000
[21]. Andy电子工程专辑,PRBS码简介[EB/OL],中国通信人。2010.11.08
[22]. Synopsys Inc. Design Ware Core XAUI PHY TSMC 45-nm LP[DB].2010
[23]. Desandoli, Lisa Ann. High speed I-O loopback testing with low speed DC test capability [P]. United States Patent 7200170
[24].田广锟.高速电路设计新技术新工艺[M].电子工业出版社2010
[25]. Guy Perry. The Fundamentals of Digital Semiconductor Testing[M].1999
[2].汪荣源.电路理论基础[M]浙江大学出版社1997.5
[3].于歆杰(译者).模拟电路[M]清华大学出版社2008
[4].毕岗.电磁场与微波[M]浙江大学出版社2006
[5].黄智伟.印制电路板(PCB)设计技术与实践[M].2009
[6]. Philippe Cauvet. Advanced High Speed I/O Test Cookbook[M].2005
[7]. Maxim.Inc. Introduction to LVDS, PECL, and CML[EB].2008
[8]. Verigy.Inc. Verigy93000 SOC Series User Training[EB].2000
[9]. Verigy.Inc. System Reference[EB].2010
[10]. Verigy.Inc.Test Method Reference[EB] 2010
[11]. Verigy.Inc. Multi-Sites Reference[EB] 2010
[12]. Justin Redd.A second look at jitter:calculating bit error rates[EB]. http://www.commSdesign.com/story/OEG20020306S0023.2001
[13].泰克中国有限公司深入剖析眼图及高速串行设计中的眼图测试[J].国外电子测量技术2011(4)
[14].杨俊峰,高速数字串行通信中的时间抖动研究[D],中国科学技术大学,2005
[15]. Trident.Inc. Moca Chip Datasheet[EB].2011
[16]. Hubert Werkmann, Verigy X-Mode Pattern Synchronization to Free Running Bit Streams[EB] 2006
[17]. IEEE.Clause 47. XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI). IEEE Std 802.3-2008 Section 4. Institute of Electrical and Electronics Engineers[S].2008
[18]. J.M.Martins Ferreira. DESIGN FOR TEST STANDARDS[M].2000
[19]. IEEE.IEEE Std 1149.1-2001[S].2001
[20]. Michael L Bushnell and Vishwani D. Agrawal. Essentials of Electronic Testing for Digital, memory & Mixed-Signal VLSI Circuits[M]. Kluwer Academic Publishers.2000
[21]. Andy电子工程专辑,PRBS码简介[EB/OL],中国通信人。2010.11.08
[22]. Synopsys Inc. Design Ware Core XAUI PHY TSMC 45-nm LP[DB].2010
[23]. Desandoli, Lisa Ann. High speed I-O loopback testing with low speed DC test capability [P]. United States Patent 7200170
[24].田广锟.高速电路设计新技术新工艺[M].电子工业出版社2010
[25]. Guy Perry. The Fundamentals of Digital Semiconductor Testing[M].1999
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