部分向量切分的LFSR重新播种测试方法
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摘要
随着系统和电路规模的增大以及芯片集成度的提高,尤其是系统芯片的出现,使得测试数据迅猛上升,施加测试的时间不断增加,自动测试设备(ATE)性能要求大幅度提高,需要更高的测试通道带宽来满足测试数据的传输。而且,因为管脚的电感和测试仪管脚费用很高,实现全速测试越来越困难。
与传统的外部测试方法相比,内建自测试(BIST)是一种更好的选择。BIST将测试模式生成,测试应用和测试响应移入到芯片自身中,从而摆脱了对昂贵的ATE的依赖,缩减了测试花费。鉴于线性反馈移位寄存器(LFSR)是工业界广泛使用的一种BIST方案,本文着重研究基于LFSR重新播种方法的测试数据压缩问题。
本文分析了一些典型的基于LFSR的测试数据压缩方法,LFSR重新播种方法中编码生成的种子的长度受测试集中测试向量确定位最大数目S_(max)的制约,因此存在硬件开销大或计算复杂等若干问题。
本文提出一种基于测试向量分块级联的LFSR重新播种方法。该方法先把测试集里含确定位位数大于某一取定值的测试向量分割成若干块,使每一块所含的确定位位数不大于取定值。并把含确定位总数少于这一取定值的连续数据块或向量级联成一个数据块。在数据块的末尾添加一位标示位来标识它是否和下一个数据块级联。使得各个数据块所含的确定位位数基本相同,提高数据压缩率并减少硬件开销。
针对确定测试集中各个测试向量包含确定位的位数有较大差异以及测试向量所含的确定位大多连续成块的特点,本文提出一种基于部分测试向量奇偶位切分的LFSR重新播种测试方法。通过奇偶切分部分确定位较多的向量,使得编码压缩的LFSR度数得到有效降低,从而提高了测试数据压缩率。与目前国际同类编码压缩方法相比,具有测试数据压缩率高,解压硬件开销低,测试数据传输协议简单等特点。
As the size and the complexity of systems on a chip continue to grow, test data volume has increased dramatically, and test application time increase. In order to apply the large volume of test data to a chip under test, the automatic test equipment (ATE) requires large memory storage and high bandwidth. Otherwise, there is increasing difficulty in performing at-speed testing due to pin inductance and high tester pin costs.
Built-in Self-test (BIST) offers a better alternative than conventional external testing methods. By moving test generation, application and test response into the chip itself, BIST eliminates the need for expensive ATE, reduces the test cost. Due to linear feedback shift registers (LFSR) is widely used by industry as BIST, this thesis is focused on the problem of test data compression based LFSR reseeding.
Afterwards several traditional schemes for improving the encoding efficiency of the basic LFSR reseeding method are analyzed. Because the size of LFSR seed depends on the maximal number of specified bits in test patterns, some schemes have high hardware overhead, and the others need complex computation.
A scheme for LFSR reseeding by syncopation and combination of test patterns is presented. Some test patterns in a test set which have more specified bits than the number that we chose are divided into blocks, and every block has less specified bits than the number. Some successive blocks which have the less specified bits than the number are combined into one block. A flag bit is added on the tail of every block to express whether the block is combined with the next block. Thus the blocks have narrow variation in their number of specified bits.
Because test vectors vary widely in their number of specified bits, and the specified bits in a vector always appear together and form some blocks, a novel scheme for increasing test data compression rate is presented. The odd bits of some vectors which have many specified bits, and the even bits of the vector are separated off. It can reduce S_(max) of the test set and the variation in number of specified bits of vectors.
The proposed methods provide greater test data compression with less hardware overhead compared to the same kind encoding schemes.
与传统的外部测试方法相比,内建自测试(BIST)是一种更好的选择。BIST将测试模式生成,测试应用和测试响应移入到芯片自身中,从而摆脱了对昂贵的ATE的依赖,缩减了测试花费。鉴于线性反馈移位寄存器(LFSR)是工业界广泛使用的一种BIST方案,本文着重研究基于LFSR重新播种方法的测试数据压缩问题。
本文分析了一些典型的基于LFSR的测试数据压缩方法,LFSR重新播种方法中编码生成的种子的长度受测试集中测试向量确定位最大数目S_(max)的制约,因此存在硬件开销大或计算复杂等若干问题。
本文提出一种基于测试向量分块级联的LFSR重新播种方法。该方法先把测试集里含确定位位数大于某一取定值的测试向量分割成若干块,使每一块所含的确定位位数不大于取定值。并把含确定位总数少于这一取定值的连续数据块或向量级联成一个数据块。在数据块的末尾添加一位标示位来标识它是否和下一个数据块级联。使得各个数据块所含的确定位位数基本相同,提高数据压缩率并减少硬件开销。
针对确定测试集中各个测试向量包含确定位的位数有较大差异以及测试向量所含的确定位大多连续成块的特点,本文提出一种基于部分测试向量奇偶位切分的LFSR重新播种测试方法。通过奇偶切分部分确定位较多的向量,使得编码压缩的LFSR度数得到有效降低,从而提高了测试数据压缩率。与目前国际同类编码压缩方法相比,具有测试数据压缩率高,解压硬件开销低,测试数据传输协议简单等特点。
As the size and the complexity of systems on a chip continue to grow, test data volume has increased dramatically, and test application time increase. In order to apply the large volume of test data to a chip under test, the automatic test equipment (ATE) requires large memory storage and high bandwidth. Otherwise, there is increasing difficulty in performing at-speed testing due to pin inductance and high tester pin costs.
Built-in Self-test (BIST) offers a better alternative than conventional external testing methods. By moving test generation, application and test response into the chip itself, BIST eliminates the need for expensive ATE, reduces the test cost. Due to linear feedback shift registers (LFSR) is widely used by industry as BIST, this thesis is focused on the problem of test data compression based LFSR reseeding.
Afterwards several traditional schemes for improving the encoding efficiency of the basic LFSR reseeding method are analyzed. Because the size of LFSR seed depends on the maximal number of specified bits in test patterns, some schemes have high hardware overhead, and the others need complex computation.
A scheme for LFSR reseeding by syncopation and combination of test patterns is presented. Some test patterns in a test set which have more specified bits than the number that we chose are divided into blocks, and every block has less specified bits than the number. Some successive blocks which have the less specified bits than the number are combined into one block. A flag bit is added on the tail of every block to express whether the block is combined with the next block. Thus the blocks have narrow variation in their number of specified bits.
Because test vectors vary widely in their number of specified bits, and the specified bits in a vector always appear together and form some blocks, a novel scheme for increasing test data compression rate is presented. The odd bits of some vectors which have many specified bits, and the even bits of the vector are separated off. It can reduce S_(max) of the test set and the variation in number of specified bits of vectors.
The proposed methods provide greater test data compression with less hardware overhead compared to the same kind encoding schemes.
引文
[1]Michael L,Bushnell,Vishwani D,Agrawal著,蒋安平 冯建华 王新安 译 超大规模集成电路测试
[2]胡瑜,韩银和,李晓维,“SOC测试”,信息技术快报,2004年第9期。
[3]Miron Abramovici,Melvin A.Breuer,Arthur D.Friedman著 李华伟 鲁巍译数字系统测试与可测试设计机械工业出版社 2006年8月
[4]Anshuman Chandra and Krislmendu Chakrabarty,"Test Resource Partitioning for SOCs",Prec.IEEE Design & Test of Computers,2001,September-October,pp.80-91.
[5]Jochen Rivoir Agilent Technologies R&D and Marketing GmbH & Co.KG "Parallel Test Reduces Cost of Test More Effectively Than Just A Cheap Tester",20th IEEE SEMI-THERM symposium.
[6]Michael L.Bushnell,D.Vishwani Agrawal."Essentials of Electronic Testing for Digital,Memory and Mixed-Signal VLSI Circuits",USA:Kluwer Academic Publishers,2000.
[7]IEEE Standard 1149.1 IEEE Standard Test Acess Port and Boundary Scan Architecture.IEEE Press,1990
[8]Chandra A,Chakrabarty K.Test Resource Partitioning for SOCs,Design & Test of Computers,IEEE Volume18,Issue 5,Sept.-Oct.2001,pp.80-91
[9]M Barber,M Loranger,et al..Test Resource Partitioning,IEEE Design & Test of Computers,17(3),July-Sept.2000,pp.12 6-132.
[10]A Jas,J Ghosh-Dastidar,and N A Touba.Scan Vector Compression/Decompression Using Statistical Coding,Proc.of IEEE VLSI Test Symposium,1999,pp.114-120.
[11]S.M.Reddy,K.Miyase,S.Kajihara,and I.Pomeranz,"On test data volume reduction for multiple scan chain designs," Proc.IEEE VLSI Test Syrup.,April 2002,pp.103-108.
[12]L.Li,K.Chakrabarty,and N.A.Touba,"Test data compression using dictionaries with selective entries and fixed-length indices," ACM Trans.Design Autom.Electr.Syst.,8(4),470-490,2003.
[13]A.Wurtenberger,C.S.Tautermann,and S.Hellebrand,"Data compression for multiple scan chains using dictionaries with corrections," Proc.IEEE Int.Test Conf.,October 2004,pp.926-935.
[14]D.A.Huffman,"A method for the construction of minimum redundancy codes," Proc. IRE,40(9),I098-1101,1952.
[15]A.Jas,J.Ghosh-Dastidar,M.Ng,and N.A.Touba,"An efficient test vector compression scheme using selective Huffman coding," IEEE Trans.Comput.-Aided Des.,22(6),797-806,2003.
[16]P.T.Gonciari,B.M.Al-Hashimi,and N.Nicolici,"Variable-length input Huffman coding for system-on-a-chip test," IEEE Trans.Comput.-Aided Des.,22(6),783-796,2003.
[17]A.Jas and N.A.Touba,"Test vector compression via cyclical scan chains and its application to testing Core-based designs," Proc.IEEE Int.Test Conf.,October 1998,pp.458-464.
[18]F.G.Wolff and C.Papachristou,"Multiscan-based test compression and hardware decompression using LZ77," Proc.IEEE Int.Test Conf.,October 2002,pp.331-339
[19]M.Knieser,F.Wolff,C.Papachdstou,D.Weyer,and D.Mclntyre,"A technique for high ratio LZW compression," Proc.Design Automation and Test in Europe,March 2003,pp.116-121.
[20]梁华国,蒋翠云,“基于交替与连续长度码的有效测试数据压缩和解压”,计算机学报,27(4),2004,pp.548-554.
[21]Anshuman Chandra,Krishnendu Chakrabarty."Test data compression and decompression based on internal scan chains and Golomb coding," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2002,21(6):715-722
[22]Anshuman Chandra,Krishnendu Chakrabarty.Test data compression and test resource Partitioning for System-on-a-Chip using Frequency-Directed Run-Length (FDR)codes.IEEE Transactions on Computers,2003,52(8):1076-1088
[23]El-Maleh,A.H.;Al-Abaji,R.H.Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression 9th International Conference on Electronics,Circuits and Systems,Volume 2,2002:449-452.
[24]Wurtenberger A,Tautermann C S,Hellebrand S."A hybrid coding strategy for optimized test data compression," Proc.IEEE International Test Conference,Charlotte,NC,USA,2003.451-459.
[25]Wang Laung-Terng,Wu Cheng-Wen,Wen Xiaoqing VLSI Test Principles and Architectures.Morgan Kaufmann 2006.
[26]刘建都,“嵌入式系统的在线自测试技术”,微电子技术,200,28(6):46-50
[27]Alfred L.Crouch著何虎,马立伟等译 数字集成电路与嵌入式内核系统的测试设计机械工业出版社,2006
[28]时万春等 现代集成电路测试技术化学工业出版社2006
[29]Hua-Guo Liang.A New Technique for Deterministic Scan-Based Buit-In Self-Test (BIST).Aachen:Shaker Verlag,2003
[30]N.A.Touba,E.J.McCluskey.Altering a Pseudo-Random Bit Sequence for Scan-Based BIST Proceedings IEEE International Test Conference,Washington,DC,1996:167-175
[31]S.Bouzebari,B.Kaminska.A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures.IEEE Transactions on Computers,1995,44(6):805-814
[32]Serra M.The analysis of one dimensional linear Cellular Automata and their aliasing properties.IEEE Trans on CAD,1990,9(7):767-778.
[33]罗刚,洪洁 细胞自动机及其在数字VLSI测试中的应用四川大学学报(工程科学版),2004,36(4):87-94
[34]H.-J.Wunderlich,G.Kiefer Bit-Flipping BIST Proceedings of the ACM/IEEE International Conference on CAD-96 1996:337-343
[35]V.K.Agarwal,E.Cerny Store and Generate Built-In Testing Approach.Proceedings of the 11~(th)International Symposium On Fault-Tolerant Computing,1981:35-40.
[36]Hua-GuoLiang,Sybille Hellebrand,Hans-Joachim Wunderlich:Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST;Proceedings IEEE International Test Conference,2001,pp.894-902
[37]B Koenemann.LFSR-Coded Test Patterns for Scan Design,Proceedings.of European Test Conference,1991:237-242.
[38]Rajski J,J Tyszer,M Kassab,N Mukherjee,R Thompson,T Kun-Han,A Hertwig,N Tamarapalli,G Mrugalski,G Eider,Q Jun.Embedded deterministic test for low cost manufacturing test.In:Proceedings of International Test Conference,Baltimore,MD,USA,2002.301-310
[39]Koenemann B,C Bamhart,B Keller,T Snethen,O Famsworth,D Wheater.A SmartBIST variant with guaranteed encoding.In:Proceedings of VLSI Test Symposium,Marina Del Rey,CA,USA,2001.325-330
[40]Hellebrand S,S Tamick,J Rajski,et al.Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers Proceedings of International Test Conference,Baltimore,MD,USA,1992.120-129
[41]Hellebrand S,J Rajski,S Tamick,et al.Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers.IEEE Transactions on Computers,1995,44(2):223-233
[42]Zacharia N,J Rasiski,J Tyszer.Decompression of test data using variable-length seed LFSRs Proceedings of VLSI Test Symposium,Princeton,N J,USA,1995.426-433
[43]Janusz Rajski,Jerzy Tyszer,Nadime Zacharia.Test data decompression for multiple scan designs with boundary scan.IEEE Transactions on Computers,1998,47(11):1188-1200
[44]C.V.Krishna,Abhijit Jas,Nur A.Touba.Test cube encoding using partial LFSR reseeding.In:Proceedings of International Test Conference,Baltimore,MD,USA,2001.885-893
[45]梁华国,聚贝勒.海伦布昂特,汉斯.耶西姆.冯特利西.一种基于折叠计数器重新播种的确定自测试方案[J].计算机研究与发展,2001,38(8):931-938
[46]梁华国,将翠云.使用双重种子压缩的混合模式自测试[J].计算机研究与发展,2004,41(1):214-220
[47]梁华国,方祥圣,将翠云,等。一种选择折叠计数状态转移的BIST方案。计算机研究与发展,2006,43(2):343-349
[48]S.Swaminathan and K.Chakrabarty On using twisted-ring counters for test set embedding in BIST,Journal of Electronic Testing:Theory and Applications,vol.17,pp.530-542,December 2001
[49]李扬,梁华国,刘军,胡志国.基于部分测试向量切分的LFSR重新播种方法.计算机辅助设计与图形学学报,第19卷第3期,2007年3月
[2]胡瑜,韩银和,李晓维,“SOC测试”,信息技术快报,2004年第9期。
[3]Miron Abramovici,Melvin A.Breuer,Arthur D.Friedman著 李华伟 鲁巍译数字系统测试与可测试设计机械工业出版社 2006年8月
[4]Anshuman Chandra and Krislmendu Chakrabarty,"Test Resource Partitioning for SOCs",Prec.IEEE Design & Test of Computers,2001,September-October,pp.80-91.
[5]Jochen Rivoir Agilent Technologies R&D and Marketing GmbH & Co.KG "Parallel Test Reduces Cost of Test More Effectively Than Just A Cheap Tester",20th IEEE SEMI-THERM symposium.
[6]Michael L.Bushnell,D.Vishwani Agrawal."Essentials of Electronic Testing for Digital,Memory and Mixed-Signal VLSI Circuits",USA:Kluwer Academic Publishers,2000.
[7]IEEE Standard 1149.1 IEEE Standard Test Acess Port and Boundary Scan Architecture.IEEE Press,1990
[8]Chandra A,Chakrabarty K.Test Resource Partitioning for SOCs,Design & Test of Computers,IEEE Volume18,Issue 5,Sept.-Oct.2001,pp.80-91
[9]M Barber,M Loranger,et al..Test Resource Partitioning,IEEE Design & Test of Computers,17(3),July-Sept.2000,pp.12 6-132.
[10]A Jas,J Ghosh-Dastidar,and N A Touba.Scan Vector Compression/Decompression Using Statistical Coding,Proc.of IEEE VLSI Test Symposium,1999,pp.114-120.
[11]S.M.Reddy,K.Miyase,S.Kajihara,and I.Pomeranz,"On test data volume reduction for multiple scan chain designs," Proc.IEEE VLSI Test Syrup.,April 2002,pp.103-108.
[12]L.Li,K.Chakrabarty,and N.A.Touba,"Test data compression using dictionaries with selective entries and fixed-length indices," ACM Trans.Design Autom.Electr.Syst.,8(4),470-490,2003.
[13]A.Wurtenberger,C.S.Tautermann,and S.Hellebrand,"Data compression for multiple scan chains using dictionaries with corrections," Proc.IEEE Int.Test Conf.,October 2004,pp.926-935.
[14]D.A.Huffman,"A method for the construction of minimum redundancy codes," Proc. IRE,40(9),I098-1101,1952.
[15]A.Jas,J.Ghosh-Dastidar,M.Ng,and N.A.Touba,"An efficient test vector compression scheme using selective Huffman coding," IEEE Trans.Comput.-Aided Des.,22(6),797-806,2003.
[16]P.T.Gonciari,B.M.Al-Hashimi,and N.Nicolici,"Variable-length input Huffman coding for system-on-a-chip test," IEEE Trans.Comput.-Aided Des.,22(6),783-796,2003.
[17]A.Jas and N.A.Touba,"Test vector compression via cyclical scan chains and its application to testing Core-based designs," Proc.IEEE Int.Test Conf.,October 1998,pp.458-464.
[18]F.G.Wolff and C.Papachristou,"Multiscan-based test compression and hardware decompression using LZ77," Proc.IEEE Int.Test Conf.,October 2002,pp.331-339
[19]M.Knieser,F.Wolff,C.Papachdstou,D.Weyer,and D.Mclntyre,"A technique for high ratio LZW compression," Proc.Design Automation and Test in Europe,March 2003,pp.116-121.
[20]梁华国,蒋翠云,“基于交替与连续长度码的有效测试数据压缩和解压”,计算机学报,27(4),2004,pp.548-554.
[21]Anshuman Chandra,Krishnendu Chakrabarty."Test data compression and decompression based on internal scan chains and Golomb coding," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2002,21(6):715-722
[22]Anshuman Chandra,Krishnendu Chakrabarty.Test data compression and test resource Partitioning for System-on-a-Chip using Frequency-Directed Run-Length (FDR)codes.IEEE Transactions on Computers,2003,52(8):1076-1088
[23]El-Maleh,A.H.;Al-Abaji,R.H.Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression 9th International Conference on Electronics,Circuits and Systems,Volume 2,2002:449-452.
[24]Wurtenberger A,Tautermann C S,Hellebrand S."A hybrid coding strategy for optimized test data compression," Proc.IEEE International Test Conference,Charlotte,NC,USA,2003.451-459.
[25]Wang Laung-Terng,Wu Cheng-Wen,Wen Xiaoqing VLSI Test Principles and Architectures.Morgan Kaufmann 2006.
[26]刘建都,“嵌入式系统的在线自测试技术”,微电子技术,200,28(6):46-50
[27]Alfred L.Crouch著何虎,马立伟等译 数字集成电路与嵌入式内核系统的测试设计机械工业出版社,2006
[28]时万春等 现代集成电路测试技术化学工业出版社2006
[29]Hua-Guo Liang.A New Technique for Deterministic Scan-Based Buit-In Self-Test (BIST).Aachen:Shaker Verlag,2003
[30]N.A.Touba,E.J.McCluskey.Altering a Pseudo-Random Bit Sequence for Scan-Based BIST Proceedings IEEE International Test Conference,Washington,DC,1996:167-175
[31]S.Bouzebari,B.Kaminska.A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures.IEEE Transactions on Computers,1995,44(6):805-814
[32]Serra M.The analysis of one dimensional linear Cellular Automata and their aliasing properties.IEEE Trans on CAD,1990,9(7):767-778.
[33]罗刚,洪洁 细胞自动机及其在数字VLSI测试中的应用四川大学学报(工程科学版),2004,36(4):87-94
[34]H.-J.Wunderlich,G.Kiefer Bit-Flipping BIST Proceedings of the ACM/IEEE International Conference on CAD-96 1996:337-343
[35]V.K.Agarwal,E.Cerny Store and Generate Built-In Testing Approach.Proceedings of the 11~(th)International Symposium On Fault-Tolerant Computing,1981:35-40.
[36]Hua-GuoLiang,Sybille Hellebrand,Hans-Joachim Wunderlich:Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST;Proceedings IEEE International Test Conference,2001,pp.894-902
[37]B Koenemann.LFSR-Coded Test Patterns for Scan Design,Proceedings.of European Test Conference,1991:237-242.
[38]Rajski J,J Tyszer,M Kassab,N Mukherjee,R Thompson,T Kun-Han,A Hertwig,N Tamarapalli,G Mrugalski,G Eider,Q Jun.Embedded deterministic test for low cost manufacturing test.In:Proceedings of International Test Conference,Baltimore,MD,USA,2002.301-310
[39]Koenemann B,C Bamhart,B Keller,T Snethen,O Famsworth,D Wheater.A SmartBIST variant with guaranteed encoding.In:Proceedings of VLSI Test Symposium,Marina Del Rey,CA,USA,2001.325-330
[40]Hellebrand S,S Tamick,J Rajski,et al.Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers Proceedings of International Test Conference,Baltimore,MD,USA,1992.120-129
[41]Hellebrand S,J Rajski,S Tamick,et al.Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers.IEEE Transactions on Computers,1995,44(2):223-233
[42]Zacharia N,J Rasiski,J Tyszer.Decompression of test data using variable-length seed LFSRs Proceedings of VLSI Test Symposium,Princeton,N J,USA,1995.426-433
[43]Janusz Rajski,Jerzy Tyszer,Nadime Zacharia.Test data decompression for multiple scan designs with boundary scan.IEEE Transactions on Computers,1998,47(11):1188-1200
[44]C.V.Krishna,Abhijit Jas,Nur A.Touba.Test cube encoding using partial LFSR reseeding.In:Proceedings of International Test Conference,Baltimore,MD,USA,2001.885-893
[45]梁华国,聚贝勒.海伦布昂特,汉斯.耶西姆.冯特利西.一种基于折叠计数器重新播种的确定自测试方案[J].计算机研究与发展,2001,38(8):931-938
[46]梁华国,将翠云.使用双重种子压缩的混合模式自测试[J].计算机研究与发展,2004,41(1):214-220
[47]梁华国,方祥圣,将翠云,等。一种选择折叠计数状态转移的BIST方案。计算机研究与发展,2006,43(2):343-349
[48]S.Swaminathan and K.Chakrabarty On using twisted-ring counters for test set embedding in BIST,Journal of Electronic Testing:Theory and Applications,vol.17,pp.530-542,December 2001
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