基于多扫描链的测试数据压缩方法研究
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摘要
超深亚微米技术的应用使得芯片的集成度大幅提高,集成电路设计正快速地向系统芯片SoC(System-On-a-Chip)设计方法转变,逐步地将各种预先设计和验证的芯核(core)集成在一个芯片上,这种基于芯核的设计风格和创新技术,大大增加了设计产量,使得在一个SoC上集成数亿个晶体管成为可能,也加快了产品投放市场的时间,但是,不断增加的芯片复杂性和测试数据量,也使芯片的测试费用不断上升,尤其是自动测试设备ATE变得越来越昂贵,测试问题已经成为SoC发展的瓶颈。
测试数据压缩是解决SoC测试问题的一种行之有效的方法,它可以用于减少所需存储的测试数据量。测试向量集经压缩(编码)后,数据量可以缩小20倍以上。测试时,压缩后的数据经过解码电路被还原为原始的测试向量,施加到被测电路完成测试。
本文所做的主要工作如下:
1.介绍了基本的SoC测试相关知识及目前主要的SoC测试方法。
2.提出了两种针对多扫描链的测试数据压缩方案:
①基于多扫描链的两维(纵向/横向)测试数据压缩方案有效降低测试的数据存储量,减少测试时间。首先,运用相容压缩技术对多扫描链环境下的测试集进行压缩,合并相容扫描链;然后,针对合并后的多扫描链测试模式,按照测试模式间差别字的多少,进行优化排序,记录相邻的差别字,并将差别字按字典方法编码进行再压缩。
②基于多扫描链的逆向折叠测试数据压缩方案是在基于折叠计数器的测试数据压缩方法的基础上,利用测试模式间的逆向折叠关系,通过一个逆向折叠种子和测试模式间的逆向距离值来记录整个测试集。在整个解压过程中本方案不需要进行种子的重播种,只利用逆向距离值实现模式间的转变,高效地述原出原测试集,这种方法有效地减少了测试数据量和测试时间。
3.设计开发了针对以上两个方案的实验程序,提供了实验结果,在采用相同实验数据的情况下,与混合码等方案的实验结果进行了比较,结果表明本文的方法明显具有更高的压缩率,同时,解压结构也较简单,因此,本文的方案拥有高效而快速的综合测试性能。
The application of Very Deep Sub-Micron (VDSM) technology increases the density of chips greatly. IC design is being quickly transformed into SoC (System-On-a-Chip) design. Various pre-designed and pre-verified cores are gradually built on a single chip ,and this design style and innovative technology based on cores enhances the output of design. Now, it is possible to build hundreds of million transistors on a SoC. Also, it takes a shorter time for product to come into the market . But, the continually increasing complexity and testing data volume make the testing cost continuously rising. Particularly, ATE(Automatic Test Equipment) is becoming more and more expensive, so the problem of testing has bottlenecked the development of SoC .The test data compression is a feasible measure to resolve the problem of SoC test. It can be used to decrease the SoC test data volume . The volume of test vector can be decrease to less than one twentieth through compressing (coding).While testing , the compressed data can be decompressed to the original test vectors with the decoding circuit, then the original test vectors are put into the CUT(circuit under test) to finish the test.The main work of the thesis are showed as following:Firstly, the introduction of the basic knowledge and the main methods of SoC test in present.Secondly, the thesis puts forward two kinds of test data compression approach for multiple scan chains:(1) Two-dimensional(vertical/horizontal) test data compression approach for multiple scan chains reduces test data volume and testing time efficiently. First, it does the vertical compression (compatible compression) for the test patterns formatted according to multiple scan chains, and then it rearranges the results to accomplish the horizontal compression for the test set by coding the different word with dictionary and marking the distance.(2) Approach of test data compression based on inverted folding counter for multiple scan chains is based on the scheme of test-data compression of folding counter. It takes advantage of the inverted folding relations between the test patterns, and records the whole test set by one inverted folding seed and the inverted folding distances between the test patterns. During the process of the decompression, it changes the patterns with inverted folding distances to decompress the test set efficiently without reseeding. This method
reduce both the test data volume and the test application time greatly.Thirdly, The design and development of the experiment programs for these two schemes . The results of experiment are shown and compared with Hybrid Codes' and other schemes', and it is evident that these two proposed approach have higher compression ratio than the others. At the same time, the decompression structure is simpler. In a word, these approaches have efficient performance in test.
测试数据压缩是解决SoC测试问题的一种行之有效的方法,它可以用于减少所需存储的测试数据量。测试向量集经压缩(编码)后,数据量可以缩小20倍以上。测试时,压缩后的数据经过解码电路被还原为原始的测试向量,施加到被测电路完成测试。
本文所做的主要工作如下:
1.介绍了基本的SoC测试相关知识及目前主要的SoC测试方法。
2.提出了两种针对多扫描链的测试数据压缩方案:
①基于多扫描链的两维(纵向/横向)测试数据压缩方案有效降低测试的数据存储量,减少测试时间。首先,运用相容压缩技术对多扫描链环境下的测试集进行压缩,合并相容扫描链;然后,针对合并后的多扫描链测试模式,按照测试模式间差别字的多少,进行优化排序,记录相邻的差别字,并将差别字按字典方法编码进行再压缩。
②基于多扫描链的逆向折叠测试数据压缩方案是在基于折叠计数器的测试数据压缩方法的基础上,利用测试模式间的逆向折叠关系,通过一个逆向折叠种子和测试模式间的逆向距离值来记录整个测试集。在整个解压过程中本方案不需要进行种子的重播种,只利用逆向距离值实现模式间的转变,高效地述原出原测试集,这种方法有效地减少了测试数据量和测试时间。
3.设计开发了针对以上两个方案的实验程序,提供了实验结果,在采用相同实验数据的情况下,与混合码等方案的实验结果进行了比较,结果表明本文的方法明显具有更高的压缩率,同时,解压结构也较简单,因此,本文的方案拥有高效而快速的综合测试性能。
The application of Very Deep Sub-Micron (VDSM) technology increases the density of chips greatly. IC design is being quickly transformed into SoC (System-On-a-Chip) design. Various pre-designed and pre-verified cores are gradually built on a single chip ,and this design style and innovative technology based on cores enhances the output of design. Now, it is possible to build hundreds of million transistors on a SoC. Also, it takes a shorter time for product to come into the market . But, the continually increasing complexity and testing data volume make the testing cost continuously rising. Particularly, ATE(Automatic Test Equipment) is becoming more and more expensive, so the problem of testing has bottlenecked the development of SoC .The test data compression is a feasible measure to resolve the problem of SoC test. It can be used to decrease the SoC test data volume . The volume of test vector can be decrease to less than one twentieth through compressing (coding).While testing , the compressed data can be decompressed to the original test vectors with the decoding circuit, then the original test vectors are put into the CUT(circuit under test) to finish the test.The main work of the thesis are showed as following:Firstly, the introduction of the basic knowledge and the main methods of SoC test in present.Secondly, the thesis puts forward two kinds of test data compression approach for multiple scan chains:(1) Two-dimensional(vertical/horizontal) test data compression approach for multiple scan chains reduces test data volume and testing time efficiently. First, it does the vertical compression (compatible compression) for the test patterns formatted according to multiple scan chains, and then it rearranges the results to accomplish the horizontal compression for the test set by coding the different word with dictionary and marking the distance.(2) Approach of test data compression based on inverted folding counter for multiple scan chains is based on the scheme of test-data compression of folding counter. It takes advantage of the inverted folding relations between the test patterns, and records the whole test set by one inverted folding seed and the inverted folding distances between the test patterns. During the process of the decompression, it changes the patterns with inverted folding distances to decompress the test set efficiently without reseeding. This method
reduce both the test data volume and the test application time greatly.Thirdly, The design and development of the experiment programs for these two schemes . The results of experiment are shown and compared with Hybrid Codes' and other schemes', and it is evident that these two proposed approach have higher compression ratio than the others. At the same time, the decompression structure is simpler. In a word, these approaches have efficient performance in test.
引文
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[5] Chandra, A.;Chakrabarty, K. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. Computers, IEEE Transactions on Volume 52, Issue 8, Aug. 2003 Page(s):1076 -1088
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[9] Kajihara. S., Pomeranz. I., Kinoshita. K., Reddy,.S.M. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 14, Issue 12, Dec. 1995 Page(s): 1496-1504
[10]Pomeranz. I., Reddy. L.N., Reddy. S.M. COMPACTEST: a method to generate compact test sets for combinational circuits. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 12, Issue 7, July 1993 Page(s):1040-1049
[11] Jas. A., Ghosh-Dastidar. J., Touba. N.A. Scan vector compression/decompression using statistical coding. VLSI Test Symposium, 1999. Proceedings. 17th IEEE 25-29 April 1999 Page(s):114-120
[12] Jas.A.,Ghosh-Dastidar.J.,Mom-Eng.Ng,Touba.N.A.An efficient test vector compression scheme using selective Huffman coding.Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on Volume 22, Issue 6, June 2003 Page(s):797 - 806
[13] Chandra.A.,Chakrabarty.K.System-on-a-chip test-data compression and decompression architectures based on internal scan chains and Golomb codes.IEEE Transactions on computer-aided design of integrated circuit & systems, vol.21,2002,pp.715-722
[14] Chandra.A.,Chakrabarty.K.System-on-a-chip test-data compression and decompression architectures based on Golomb codes.Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 20, Issue 3, March 2001 Page(s):355-368
[15] Frequency-directed run-length(FDR) codes with application to system-on-a-chip test data compression Chandra, A.;Chakrabarty, K.;Proc,IEEE VLSI Test Symposium, 2001, pp,42-47
[16] A.Jas and N.A.Touba, Test vector decompression via cyclical scan chain and its application to testing core-based designs Proc.of IEEE International Test Conference (ITC), 1998
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[18] 梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压.计算机学报.第27卷第4期,2004年4月
[19] 梁华国,聚贝勒.海伦布昂特,汉斯-耶西姆.冯特利西.一种基于折叠计数器重新播种的确定自测试方案.计算机研究与发展,2001,38(8)
[20] LIANG Huaguo,S.Hellebrand,H.-J.Wunderlich. A Mixed-Mode BIST Scheme Based on Folding Comression. Journal of Computer Science and Technology, Vol 17 No 2, 2002
[21] Huaguo Liang, Cuiyun Jiang.Sharing BIST with Multiple Cores for System-on-a-chip, Proc. of the 12th Asian Test Symposium, 2003
[22] Xiaowei Li and P.Y.S.Cheng. A Loop-Based Apparatus for At-Speed Self-Testing. Journal of Computer Science and Technology, Vol. 16,No.3,2001,pp.278-285
[23] Xiaowei Li, P.Y.S.Cheng and H.Fujiwara. LFSR-Based Deterministic TPG for Two Pattern Testing. Journal of Electronic Testing: Theory and Application,Vol.16, No. 5, 2000,pp.419-426
[24] 李兆麟,叶以正,毛志刚:基于多扫描链的内建自测试技术中的测试向量生成,计算机学报,第24卷第4期,2001年4月
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