系统芯片测试优化关键技术研究
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摘要
随着集成电路工艺技术和设计方法的提高,集成电路的规模越来越大,使得原来要由多个芯片才可以实现的复杂系统被集成在单个芯片上成为可能。在这种背景下,系统芯片(SOC, System-on-a-Chip)应运而生。SOC技术采用IP核复用的设计方法,将整个系统映射到单个芯片上,既可以加快开发进度,又可以缩小产品体积、提高系统性能,近年来得到了广泛的应用。
然而随着SOC集成的IP核数目的增多,其功能越来越复杂,SOC的测试数据量、测试功耗也随之急剧增加,对各个IP核进行测试访问也变得更加困难,这些都为SOC测试带来更大的挑战。
本文在研究SOC测试结构的基础上,对当前SOC测试中存在的问题进行分析,重点针对测试数据量大、测试功耗高和测试时间长这三个关键问题进行研究,提出了相应的解决方法,并在ISCAS’89和ITC’02标准测试集上进行仿真实验,验证了方法的有效性和实用价值。
本文的主要研究内容和成果如下:
1.对基于编码的测试压缩方法进行研究,针对测试数据预处理中差分操作后测试集中数据“1”的比例较高的问题,提出了基于蚁群算法的测试向量排序算法,以进一步提高压缩效率;针对目前大多数编码压缩方法仅针对测试数据中的0游程进行压缩的现状,提出了一种同时考虑0游程与1游程的变游程编码方法,该方法在应用中不需要对原始数据作差分变换,因此能在提高压缩效率的同时减少解码的硬件开销;
2.研究适用于多扫描链IP核的测试数据压缩方法,在分析字典方法基本原理的基础上,对其进行改进,提出了压缩比更高的基于频率指示索引字典的多扫描链测试数据压缩算法;本文利用测试数据间的重复性,提出了基于子向量重复性的测试数据压缩算法;仿真实验表明,两种多扫描链测试压缩算法都能够取得较高的压缩效率;
3.在分析测试功耗产生原因的基础上,本文提出了基于扫描链冻结的测试功耗优化方法,以降低扫描测试中触发器的无用跳变次数,进而降低扫描测试功耗;
4.针对IP核串行测试封装结构造成测试功耗过高的问题,利用测试向量中的完全重叠和部分重叠现象,本文提出基于部分重叠向量的并行测试封装结构,以解决串行封装结构测试功耗过高的问题,仿真实验证明了该方法的有效性;
5.在研究测试访问机制(TAM, Test Access Mechanism)结构的基础上,讨论TAM结构优化与测试调度问题,提出了基于Two-Stage GA的测试调度算法,该方法采用灵活的测试总线分配方案,使得SOC系统级测试时间得到进一步降低。
With the continuous improvements in the semiconductor manufacturing technology, the integrated circuits is becoming more and more complex, and tens or even hundreds of millions of transistors can be integrated into a silicon die, which promotes the advent of System-On-a-Chip (SOC). The design of SOC mainly adopts the technique of reusable Intellectual-Property (IP) cores, and maps the whole system to a single chip, so it can shorten the time to market, and lower the cost of chips. SOC can greatly reduce the size of products and improve the performance of the system by reducing the delay between chips. Therefore, it has been widely used in many industrial fields in recent years.
However, with the increase of the number of IP cores integrated in SOC, the functions of SOC are becoming more complex. Therefore, SOC test data volume and test power consumption grow rapidly, and test access is also more difficult. All these cases bring more challenges to SOC test.
Based on the SOC test architecture, the problems exist in SOC testing domain are discussed. This dissertation aims at solving the problems of huge test data, high power dissipation and long test time appearing in SOC testing, and makes research in test compression, test power optimization and test scheduling.
The main contents and research contributions of this dissertation are as follows:
1. Test compression methods based on coding are firstly discussed. In order to reduce the percentage of“1”in the test set after difference operation, a test vector reorder algorithm based on ACO optimization is proposed. At present, most test compression methods based on coding adopt the idea of dealing with runs of 0’s. A test compression approach based on Variable-Run-Length code is proposed in this dissertation. Both runs of 0’s and runs of 1’s in test data stream are mapped to codeword so as to reduce the number of short runs and improve compression ratio.
2. Test compression methods for multi-scan chains are studied. A novel test compression method using dictionaries with frequency-directed indices (FDI) is proposed to reduce the test data volume in SOCs. In the meanwhile, considering repetition between test vectors, a test compression algorithm based on sub-vector repetition is also proposed. Experimental results show that the two methods are both effective in reducing test data volumes.
3. Based on the possible reasons of high power dissipation, an efficient test power optimization algorithm based on scan chain frozen is proposed. This method reduces the switching activities so as to reduce scan test power.
4. In order to decrease the test power consumption when using serial test wrapper, a parellel test wrapper architecture is proposed in this dissertation. The new wrapper makes use of the superposition among test vectors. Experimental results show the validity of the proposed method.
5. TAM optimization and SOC test scheduling problem are studied in this dissertation. A test scheduling algorithm based on two-stage GA is proposed to co-optimized TAM partitioning and test scheduling. Experimental results show the proposed algorithm is effective in reducing SOC test time.
然而随着SOC集成的IP核数目的增多,其功能越来越复杂,SOC的测试数据量、测试功耗也随之急剧增加,对各个IP核进行测试访问也变得更加困难,这些都为SOC测试带来更大的挑战。
本文在研究SOC测试结构的基础上,对当前SOC测试中存在的问题进行分析,重点针对测试数据量大、测试功耗高和测试时间长这三个关键问题进行研究,提出了相应的解决方法,并在ISCAS’89和ITC’02标准测试集上进行仿真实验,验证了方法的有效性和实用价值。
本文的主要研究内容和成果如下:
1.对基于编码的测试压缩方法进行研究,针对测试数据预处理中差分操作后测试集中数据“1”的比例较高的问题,提出了基于蚁群算法的测试向量排序算法,以进一步提高压缩效率;针对目前大多数编码压缩方法仅针对测试数据中的0游程进行压缩的现状,提出了一种同时考虑0游程与1游程的变游程编码方法,该方法在应用中不需要对原始数据作差分变换,因此能在提高压缩效率的同时减少解码的硬件开销;
2.研究适用于多扫描链IP核的测试数据压缩方法,在分析字典方法基本原理的基础上,对其进行改进,提出了压缩比更高的基于频率指示索引字典的多扫描链测试数据压缩算法;本文利用测试数据间的重复性,提出了基于子向量重复性的测试数据压缩算法;仿真实验表明,两种多扫描链测试压缩算法都能够取得较高的压缩效率;
3.在分析测试功耗产生原因的基础上,本文提出了基于扫描链冻结的测试功耗优化方法,以降低扫描测试中触发器的无用跳变次数,进而降低扫描测试功耗;
4.针对IP核串行测试封装结构造成测试功耗过高的问题,利用测试向量中的完全重叠和部分重叠现象,本文提出基于部分重叠向量的并行测试封装结构,以解决串行封装结构测试功耗过高的问题,仿真实验证明了该方法的有效性;
5.在研究测试访问机制(TAM, Test Access Mechanism)结构的基础上,讨论TAM结构优化与测试调度问题,提出了基于Two-Stage GA的测试调度算法,该方法采用灵活的测试总线分配方案,使得SOC系统级测试时间得到进一步降低。
With the continuous improvements in the semiconductor manufacturing technology, the integrated circuits is becoming more and more complex, and tens or even hundreds of millions of transistors can be integrated into a silicon die, which promotes the advent of System-On-a-Chip (SOC). The design of SOC mainly adopts the technique of reusable Intellectual-Property (IP) cores, and maps the whole system to a single chip, so it can shorten the time to market, and lower the cost of chips. SOC can greatly reduce the size of products and improve the performance of the system by reducing the delay between chips. Therefore, it has been widely used in many industrial fields in recent years.
However, with the increase of the number of IP cores integrated in SOC, the functions of SOC are becoming more complex. Therefore, SOC test data volume and test power consumption grow rapidly, and test access is also more difficult. All these cases bring more challenges to SOC test.
Based on the SOC test architecture, the problems exist in SOC testing domain are discussed. This dissertation aims at solving the problems of huge test data, high power dissipation and long test time appearing in SOC testing, and makes research in test compression, test power optimization and test scheduling.
The main contents and research contributions of this dissertation are as follows:
1. Test compression methods based on coding are firstly discussed. In order to reduce the percentage of“1”in the test set after difference operation, a test vector reorder algorithm based on ACO optimization is proposed. At present, most test compression methods based on coding adopt the idea of dealing with runs of 0’s. A test compression approach based on Variable-Run-Length code is proposed in this dissertation. Both runs of 0’s and runs of 1’s in test data stream are mapped to codeword so as to reduce the number of short runs and improve compression ratio.
2. Test compression methods for multi-scan chains are studied. A novel test compression method using dictionaries with frequency-directed indices (FDI) is proposed to reduce the test data volume in SOCs. In the meanwhile, considering repetition between test vectors, a test compression algorithm based on sub-vector repetition is also proposed. Experimental results show that the two methods are both effective in reducing test data volumes.
3. Based on the possible reasons of high power dissipation, an efficient test power optimization algorithm based on scan chain frozen is proposed. This method reduces the switching activities so as to reduce scan test power.
4. In order to decrease the test power consumption when using serial test wrapper, a parellel test wrapper architecture is proposed in this dissertation. The new wrapper makes use of the superposition among test vectors. Experimental results show the validity of the proposed method.
5. TAM optimization and SOC test scheduling problem are studied in this dissertation. A test scheduling algorithm based on two-stage GA is proposed to co-optimized TAM partitioning and test scheduling. Experimental results show the proposed algorithm is effective in reducing SOC test time.
引文
[1] G. Moore. Progress in Digital Integrated Electronics. International Electron Device Meeting (IEDM) Tech. Digest, 1975:11~13
[2] SIA, International Technology Roadmap for Semiconductors. http://public.itrs.net/files/1999_SIA_Roadmap/home.htm, 1999
[3] D. Buss, B. L Evans, J. Belly, W. Krenik, B. Haroun, D. Leipold, K. Maggio, J. Y Yang, T. Moise. SOC CMOS Technology for Personal Internet Products. IEEE Transactions on Electron Devices. 2003,50(3):546~556
[4] B. Stabernack, G. Von Colln. An MPEG-4 Video Code SOC for Mobile Multimedia Application. IEEE International Conference on Consumer Electronics. Sydney, Australia, 2003:248~249
[5] H. Nagle, S. C Roy, C. F Hawkins, M. G McNamer, R. R Fritzemeier. Design for Testability and Built-in Self-test: a Review. IEEE Trans. on Industrial Electronics. 1989,36(2):129~140
[6] N. S Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S Hu, M. J Irwin, M. Kandemir, V. Narayanan. Leakage Current: Moore’s Law Meets Static Power. IEEE Trans. On Computers. 2003,36(12):68~75
[7] C. Henry, C. Larry, H. Merrill. Surviving the SOC Revolution: a Guide to Platform-based Design. USA: KLUWER Academic Publishers. 1999:2~6
[8] R. Rochit. System-on-a-chip: Design and Test. USA: Advantest America R&D Center, Inc. 2000:3~6
[9]汪健. SoC设计的关键技术.集成电路通讯. 2006,24(1):1~10
[10]陆思安.可复用IP核以及系统芯片SOC的测试结构研究.浙江大学博士学位论文. 2003:2~3
[11]李加元,成立,王振宇,李华乐,贺星.系统芯片设计中的可复用IP技术.半导体技术. 2006,31(1):15~48
[12] M. J Y Willaims, J. B Angell. Enhancing Testability of Large-Scale Integreated Circuits via Test Points and Additional Logic. IEEE Trans. On Computers. 1973,C-22(1):46~60
[13] E. B Eichelberger, T. W Williams. A Logic Design Structure for LSITestability. Proceedings of the 14th design automation conference. New Orleans, LA, USA, 1977:462~468
[14] K. T Cheng, V. D Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Trans. On Computers. 1990,39(4):544~548
[15] IEEE Standard 1149.1-2001, IEEE Standard Test Access Port and Boundary-scan Architecture. IEEE. 2001
[16] E. J McCluskey. Built-in Self-Test Structures. IEEE Design&Test of Computers. 1985,2(2):29~36
[17]现代集成电路测试技术.化学工业出版社. 2006:16~17
[18] C. Timoc, M. Buehler, T. Griswold, C. Pina, F. Scott, L. Hess. Logical Models of Physical Failures. Proceedings of IEEE International Test Conference. Philadelphia, PA, USA, 1983:546~553
[19] J. P Roth. Diagnosis of Automata Failures: A Calculus and a Method. IBM Journal of Research and Devlopment. 1966,10(4):278~291
[20] J. P Roth, W. G Bouricius, P. R Scheider. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Transactions on Electronic Computers. 1967,EC-16(10):567~580
[21] P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers. 1981,C-30(3):215~222
[22] H. Fujiwara, T. Shimono. On the Acceleration of Test Pattern Algorithms. IEEE Transactions on Computers. 1983, C-32(12):1137~1144
[23] T. M Niermann, J. H Patel. HITEC: A Test Generation Package for Sequential Circuits. Proceedings of IEEE European Design Automation Conference. Amsterdam, Netherlands, 1991:214~218
[24] H. K Lee, D. S Ha. Atalanta: an Efficient ATPG for Combinational Circuits. Technical Report. Department. of Electrical Engineer, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA, 1993:93~112
[25] I. Hamzaoglu, J. H. Patel. Test Set Compaction Algorithms for Combinational Circuits. Proceedings of IEEE International Conference on Computer-Aided Design. San Jose, CA, USA, 1998:283~289
[26] I. Hamzaoglu, J. H Patel. New Techniques for Deterministic Test PatternGeneration. Proceedings of IEEE VLSI Test Symposium. Monterey, CA, USA, 1998:446~452
[27] P. H Bardell, W. H Mcanney. Self-testing of Multiple Logic Modules. Proceedings of IEEE International Test Conference. Philadelphia, PA, USA, 1982:200~204
[28] D. Xiang, M. Chen, J. Sun, H. Fujiwara. Improving Test Effectiveness of Scan-based BIST by Scan Chain Partitioning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005, 24(6):916~927
[29]陈朝阳,张伸,沈绪榜.一种改进的SRAM并行BIST电路设计.系统工程与电子技术. 2005, 27(1):159~161
[30] C. L Nan, J. W Sying, H. F Yu. Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2006, 25(11):2586~2594
[31] C. Zoellin, H. J Wunderlich, N. Maeding, J. Leenstra. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. IEEE International Test Conference. Santa Clara, CA, USA, 2006:1~8
[32] Y. Zorian, E. J Marinissen, S. Dey. Testing Embedded Core based System Chips. IEEE Int Test Conf. Washington DC, USA, 1998:130~143
[33] D. Bhattacharya. Hierarchical Test Acess Architecture for Embedded Cores in an Intergrated Circuit. IEEE Proc 16th VLSI Test Symp. Monterey, CA, USA, 1998:8~14
[34] I. Ghosh. N. K Jha, S. Dey. A Low Overhead Design for Testability and Test Generation Technique for Core-based Systems-on-a-chip. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 1999,18(11):1661~1676
[35] E. J Marinissen, K. Kuiper, C. Wouters. Testability and Test Protocol Expansion in Hierarchical Macro Testing. European Test Conference. Rotterdam, Netherlands, 1993:28~36
[36] P. Varma, S. Bhatia. A Structured Test Re-use Methodology for Core-based System Chips. IEEE International Test Conference. Washington DC, USA, 1998:294~302
[37] M. Benabdenbi, W. Maroufi, M. Marzouki. Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism. Proc Design, Automation and Test in European Conference and Exhibition. Munich, Germany, 2001:150~155
[38] E. J Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, C. Wouters. A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores. Proceedings of IEEE International Test Conference. Washington DC, USA, 1998:284~293
[39] IEEE P1500 General Working Group Website. IEEE P1500 Standards for Embedded Core Test [EB/OL]. http://grouper.ieee.org/groups/1500
[40]张颖,吴宁.基于SOC测试的IEEE P1500标准.电子测量技术. 2007, 30(5):119~121
[41]韩银和,胡瑜,董婕,王伟,李华伟,李晓维.数字电路测试压缩方法.信息技术快报. 2006,4(1):30-39
[42] E. M Rudnick, J. H Patel. Efficient Techniques for Dynamic Test Sequence Compaction. IEEE Transactions on Computers. 1999,48(3):323~330
[43] I. Hamzaoglu, J.H.Patel. Test Set Compaction Algorithms for Combinational Circuits. IEEE Transactions on Computer-Aided of Integrated Circuits and Systems. 2000,19(8):957~963
[44] I. Pomeranz, S. M. Reddy. Static Test Compaction for Multiple Full-scan Circuits. IEEE International Conference on Computer Design: VLSI in Computers and Processors. San Jose, CA, United States, 2003:393~396
[45]俞龙江,彭喜源,彭宇.基于蚁群算法的测试集优化.电子学报. 2003, 31(8):1178~1181
[46] A. Chandra, K. Chakrabarty. System-on-a-chip Test-data Compression and Decompression Architectures based on Golomb Codes. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2001,20(3):355~368
[47] A. Chandra, K. Chakrabarty. Test Data Compression and Decompression Based on Internal Scan Chains and Golomb Coding. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2002, 21(6):715~722
[48] A. Chandra, K. Chakrabarty. Frequency-directed Run-length Codes withApplication to System-on-a-chip Test Data Compression. Proceedings of the IEEE VLSI Test Symposium. Marina del Rey, CA, USA, 2001:42~47
[49] L. Li, K. Chakrabarty. On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression. Journal of Electronic Testing: Theory and Applications. 2004, 20(6):667~670
[50] A. H El-Maleh, R. H Al-Abaji. Extended Frequency-directed Run-length Codes with Improved Application to System-on-a-chip Test Data Compression. International Conference on Electronics, Circuits and System. Dubrovnik, Croatia, 2002:449~452
[51] Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A.Touba. An Efficient Test Vector Compression Scheme Using Selective Huffman Coding. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2003, 22(6):797~806
[52] S. Cho, J. Song, H. Yi, S. Park. Hybrid Test Data Compression Technique for SOC Scan Testing. IEEE International SOC Conference. Herndon, VA, United States, 2005:69~72
[53] P. T Gonciari, B. M Al-Hashimi, N. Nicolici. Variable-length Input Huffman Coding for System-on-a-chip Test. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2003, 22(6):783~796
[54] M. Nourani, M. Tehranipour. RL-Huffman Encoding for Test Compression and Power Reduction in Scan Applications. IEEE International Symposium on Circuits and Systems. Vancouver, BC, Canada, 2005:11681~11684
[55] Y. Doi, S. Kajihara, X. Q Wen, L. Li, K. Chakrabarty. Test Compression for Scan Circuits Using Scan Polarity Adjustment and Pinpoint Test Relaxation. Proceedings of the 2005 Conference on Asia and South Pacific Design Automation. Shanghai, China, 2005:59~64
[56] L. Lingappan, S. Ravi, A. Raghunathan, N. K Jha, S. T Chakradhar. Test Volume Reduction in Systems-on-a-chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2006,25(10):2193~2205
[57]徐磊,孙义和.关于VLSI测试数据的自适应压缩算法(SAC).中国科技论文在线. http://www.paper.edu.cn
[58]韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法.电子学报. 2004,32(8):1346~1350
[59]梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压.计算机学报. 2004,27(4):548~554
[60] F. C Wolff, C. Papachristou. Multiscan-based Test Compression and Hardware Decompression using LZ77. IEEE International Test Conference. Baltimore, MD, United States, 2002:331~339
[61] M. J Knieser, F. G Wolff, C. A Papachristou, D. J Weyer, D. R Mcintyre. A Technique for High Ratio LZW Compression. Design, Automation and Test in European Conference and Exhibition. Munich, Germany, 2003:116~121
[62] L. Li, K. Chadrabarty. Test Data Compression using Dictionaries with Fixed-length Indices. IEEE VLSI Test Symposium. Napa Valley, CA, 2003:219~224
[63] A. Wurtenberger, C. S Tautermann, S. Hellebrand. Data Compression for Multiple Scan Chains using Dictionaries with Corrections. International Test Conference. Charlotte, NC, United States, 2004:926~935
[64] M. Tehranipoor, M. Nourni, K. Chakrabarty. Nine-coded Compression Technique for Testing Embedded Cores in SoCs. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems. 2005,13(6):719~731
[65] S. P Lin, C. L Lee, J. E Chen, J. J Chen, K. L Luo, W. C Wu. A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Transactions on Very Large Scale Intergration Systems. 2007,15(7):767~776
[66] Y. Shi, N. Togawa, S. Kimura, M. Yanagisawa, T. Ohtsuki. FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction. Proceedings of the Asia and South Pacific Design Automation Conference. Yokohama, Japan, 2006: 653-658
[67] H. X Tang, S. M Reddy, I. Pomeranz. On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. IEEE International Test Conference. Charlotte, NC, United States, 2003:1079~1088
[68]于静,梁华国,蒋翠云.基于多扫描链相容压缩的距离标记压缩方法.合肥工业大学学报(自然科学版). 2006,29(1):5~9
[69]陶珏辉,梁华国,张磊.多扫描链测试集的分组标准向量压缩法.计算机辅助设计与图形学学报. 2007,19(6):686~691
[70] L. Li, K. Chakrabarty, S. Kajihara, S. Swaminathan. Efficient Space/Time Compression to Reduce Test Data Volume and Testing for IP Cores. Proceedings of the 18th International Conference on VLSI Design. Kolkata, India, 2005:53-58
[71] Q. Xu, N. Nicolici. Resource-constrained System-on-a-chip Test: a Survey. IEE Proceedings: Computers and Digital Techniques. 2005,152(1):67~81
[72] K. Omar, B. L Michael. Spectral Analysis for Statistical Response Compaction during Built-in Self-testing. Proceedings of International Test Conference. Charlotte, NC, United States, 2004:67~76
[73] T. Garbolino, M. Kopec, K. Gucwa, A. Hlawiczka. Detection, Localization and Identification of Interconnection Faults using MISR Compactor. IEEE Desing and Diagnostics of Electronic Circuits and systems. Praque, Czech Republic, 2006:228~229
[74] C. Santanu, Prashant. Zero Aliasing Space Compaction with Cellular Automata. IETE Journal of Research. 2004,50(6):425~431
[75] C. Krishnendu, H. P John. Test Response Compaction using Multiplexed Parity Trees. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 1996,15(11):1399~1408
[76]谢永乐,孙秀斌,王玉文,胡兵,陈光瑀. IP芯核测试响应的零混叠空间压缩.仪器仪表学报. 2005,26(4):395~398
[77] S. Mitra, K. S Kim. X-Compact: An Efficient Response Compaction Technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2004, 23(3):421~432
[78]韩银和.数字电路测试压缩方法研究.中国科学院研究生院博士学位论文. 2005
[79] J. Rajski, J. Tyszer, C. Wang, S. M Redd. Finite Memory Test Response Compactors for Embedded Test Applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005, 24(4):622~634
[80] Y. Han, Y. Hu, H. Li, X. Li. Theoretic Analysis and Enhanced X-Tolerance of Test Response Compact based on Convolutional Code. Proceedings ofIEEE Asia and South Pacific Design Automation Conference. Shanghai, China, 2005:53~58
[81] P. Girard. Survey of Low-power Testing of VLSI Circuits. IEEE Design and Test of Computers. 2002,19(3):82~92
[82]王伟,李晓维,张佑生,方芳.芯片测试中的功耗控制技术.第四届中国测试学术会议论文集. 2006:240~244
[83] S. Gerstendrfer, H. J Wunderlich. Minimized Power Consumption for Scan-based BIST. Journal of Electronic Testing: Theory and Applications. 2000,16(3):202~212
[84] F. Corno, P. Prinetto, M. Rebaudengo, M. S Reorda. Test Pattern Generation Methodology for Low Power Consumption. Proceedings of the IEEE VLSI Test Symposium. Monterey, CA, USA, 2004:453~457
[85] P. Girard, C. Landrault, S. Pravossoudovitch, D. Severac. Reducing Power Consumption during Test Application by Test Vector Ordering. IEEE International Symposium on Circuits and Systems. Monterey, CA, USA, 1998:296~299
[86] X. Kavousianos, D. Bakalis, M. Bellos, D. Nikolos. An Efficient Test Vector Ordering Method for Low Power Testing. Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design. Lafayette, LA, United States, 2004:285~288
[87] W. D Tseng. Scan Chain Ordering Technique for Switching Activity Reduction during Scan Test. IEE Proceedings on Computers and Digital Techniques. 2005,152(5):609~617
[88] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch. Efficient Scan Chain Design for Power Minimization during Scan Testing under Routing Constraint. IEEE International Test Conference. Charlotte, NC, United States, 2003:488~493
[89] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, A. Virazel. Design of Routing-constrained Low Power Scan Chains. Design, Automation and Test in Europe Conference and Exhibition. Paris, France, 2004:16~20
[90] X. L Huang, J. L Huang. A Routability Constrained Scan Chain Ordering Technique for Test Power Reduction. Proceedings of the Asia and SouthPacific Design Automation Conference. Yokohama, Japan, 2006:648~652
[91] A. Al-Yamani, N. Devta-Prasanna, A. Gunda. Should Illinois-Scan Based Architectures be Centralized or Distributed? IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Monterey, CA, United States, 2005:406~414
[92] P. Rosinger, B. M Al-Hashimi, N. Nicolici. Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2004, 23(7):1142~1153
[93] A. Al-Yamani, N. Devta-Prasanna, E. Chmelar, M. Grinchuk, A. Gunda. Scan Test Cost and Power Reduction through Systematic Scan Reconfiguration. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2007,26(5):907~918
[94] S. Ozgur, O. Alex. Modeling Scan Chain Modifications for Scan-in Test Power Minimization. IEEE International Test Conference. Charlotte, NC, United States, 2003:602~611
[95]李佳,胡瑜,李晓维,王伟. SCANGIN:一种降低扫描测试中动态功耗的方法.计算机辅助设计与图形学学报. 2006,18(9):1391~1396
[96] R. Sankaralingarn, B. Pouya, N. A Touba. Reducing Power Dissipation during Test using Scan Chain Disable. Proceedings of IEEE VLSI Test Symposium. Marina Del Rey, CA, 2001:319~324
[97]胡殿伟,向东.采用时钟屏蔽策略降低测试功耗.清华大学学报(自然科学版), 2007,47(7):1216~1219
[98] S. Wang, S. K Gupta. DS-LFSR: A New BIST TPG for Low Heat Dissipation. IEEE International Test Conference. Washington DC, USA, 1997:848~857
[99] F. Corno, M. Rebaudengo, M. S Reorda, G. Squillero, M. Violante. Low Power BIST via Non-Linear Hybrid Cellular Automata. Proceedings of 18th IEEE VLSI Test Symposium. Montreal, Canada, 2000:29-34
[100] K. Chakrabarty. Test Scheduleing for Core-based Systems using Mixed-integer Linear Programming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2000,19(10):1163~1174
[101] K. Chakrabarty. Optimal Test Access Architectures for System-on-a-chip.ACM Trans. Design Automation of Electronic System. 2001, 6(1):26~49
[102] E. Z Sadat, A. Ivanov. Design of an Optimal Test Access Architecture using a Genetic Algorithm. Proceedings of the Asian Test Symposium. Kyoto, 2001:205~210
[103]雷加,方刚.一种基于遗传算法的SOC测试调度方法.仪器仪表学报. 2007,28(4):15~17
[104]张永光,徐元欣,董斌,王匡.基于芯核的SOC测试调度.江南大学学报(自然科学版), 2005,4(2):129~133
[105]詹谨瑜,熊光泽.系统级芯片测试调度最优总线指定方法.计算机集成制造系统. 2006,12(10):1693~1697
[106] D. Zhao, S. J Upadhyaya. A Generic Resource Distribution and Test Scheduling Scheme for Embedded Core-Based SoCs. IEEE Transactions on Instrumentation and Measurement. 2004,53(2):318~329
[107] H. Yu, W. T Cheng, C. C Tsai, N. Mnkherjee, O. Samman, Y. Zaidan, S. M Reddy. Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design. Proceedings of the Asian Test Symposium. Kyoto, 2001:265~270
[108] Z. Wei, S. M Reddy, I. Pomeranz, H. Yu. SOC Test Scheduling using Simulated Annealing. Proceedings of IEEE VLSI Test Symposium. Napa Valley, California, 2003:325~330
[109] Y. Xia, M. Chrzanowska-Jeske, B. Wang. Core-based SOC Test Scheduling using Evolutionary Algorithm. Evolutionary Computation. IEEE/ACM International Conference on Computer-Aided Design. San Jose, CA, United States, 2003:1716~1732
[110] J. Y. Wuu, Tung-Chieh Chen, Yao-Wen Chang. SoC Test Scheduling using the B-Tree Based Floorplanning Technique. Proceedings of IEEE Asia and South Pacific Design Automation Conference. Shanghai, China, 2005:1188~1191
[111]杨军,罗岚.基于TCG图和模拟退火算法的SOC测试调度.电路与系统学报. 2006,11(5):37~43
[112] A. Chandra, K. Chakrabarty. A Unified Approach to Reduce SOC Test Data Volume, Scan Power and Testing Time. IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems. 2003,22(3):352~362
[113] D. Salomon. Data Compression: The Complete Reference. Springer-Verlag New York, Inc, New York, NY. 2000: 13~18
[114] J. Ziv, A. Lempel. A Universal Algorithm for Sequential Data Compression. IEEE Trans. on Information Theory. 1977,23(3):337~343
[115] C. J Tseng, D. P Siewiorek, Automated Synthesis of Data Paths in Digital Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1986,5(3):379~395
[116] H. Weste, K. Eshraghian. Principles of CMOS VLSI Design: A Systems Perspective. Addison Wesley Publication Company, Second Edition, 1992:48~51
[117] R. Sankaralingam, R. P Oruganti, N. A Touba. Static Compaction Techniques to Control Scan Vector Power Dissipation. IEEE VLSI Test Symposium. Montreal, Canada, 2000:35~40
[118]王伟,韩银和,胡瑜,李晓维,张佑生. SoC测试中低成本、低功耗的芯核包装方法.计算机辅助设计与图形学学报. 2006,18(9):1397~1402
[119] J. Aerts, E. J Marinissen. Scan Chain Design for Test Time Reduction in Core-based System Chips. Proceedings IEEE International Test Conference. Washington, DC, USA, 1998 :448~457
[120] I. Vikram, C. Krishnendu, J. M Erik. Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. International Test Conference. Baltimore, MD, USA, 2001:1023~1032
[121] Dan Zhao, Shambhu Upadhyaya, Dynamically Partitioned Test Scheduling With Adaptive TAM Configuration for Power-Constrained SoC Testing. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2005, 24(6):956~965
[122] C. P Su, C. W Wu. A Graph-based Approach to Power Constrained SOC Test Scheduling. Journal of Electronic Testing: Theory and Applications. 2004,20(1):45~60
[123] K. Chakrabarty, V. Iyengar, M. D Krasniewski. Test Planning for Modular Testing of Hierarchical SOCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005,24(3):435~447
[124] Q. M Zhou, K. J Balakrishnan. Test Cost Reduction for SoC using a Combined Approach to Test Data Compression and Test Scheduling. Design,Automation and Test in Europe Conference and Exhibition. Nice Acropolis, France, 2007:1~6
[125]邢问训,谢金星.现代优化计算方法(第2版).清华大学出版社. 2005 :113~125
[126] X. PTang, D. F Wong. A Fast Algorithm for Block Placement based on Sequence Pair, 2001 conference on Asia South Pacific design automation, Yokohama, Japan, 2001 :521~526
[127] Y. Huang, S. M Reddy, W. T Cheng, P. Reuter, N. Mukherjee, C. C Tsai, O. Samman, Y. Zaidan. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. IEEE International Test Conference. Baltimore, MD, USA, 2002:74~82
[128] V. Iyengar, K. Chakrabarty, E. J Marinissen. Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Tran. On Computers. 2003,52(12):1619~1632
[129] Y. Xia, M. C Jeske, B. Wang, M. Jeske, Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. IEEE/ACM International Conference on Computer-Aided Design. San Jose, CA, United States, 2003:100~105
[2] SIA, International Technology Roadmap for Semiconductors. http://public.itrs.net/files/1999_SIA_Roadmap/home.htm, 1999
[3] D. Buss, B. L Evans, J. Belly, W. Krenik, B. Haroun, D. Leipold, K. Maggio, J. Y Yang, T. Moise. SOC CMOS Technology for Personal Internet Products. IEEE Transactions on Electron Devices. 2003,50(3):546~556
[4] B. Stabernack, G. Von Colln. An MPEG-4 Video Code SOC for Mobile Multimedia Application. IEEE International Conference on Consumer Electronics. Sydney, Australia, 2003:248~249
[5] H. Nagle, S. C Roy, C. F Hawkins, M. G McNamer, R. R Fritzemeier. Design for Testability and Built-in Self-test: a Review. IEEE Trans. on Industrial Electronics. 1989,36(2):129~140
[6] N. S Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S Hu, M. J Irwin, M. Kandemir, V. Narayanan. Leakage Current: Moore’s Law Meets Static Power. IEEE Trans. On Computers. 2003,36(12):68~75
[7] C. Henry, C. Larry, H. Merrill. Surviving the SOC Revolution: a Guide to Platform-based Design. USA: KLUWER Academic Publishers. 1999:2~6
[8] R. Rochit. System-on-a-chip: Design and Test. USA: Advantest America R&D Center, Inc. 2000:3~6
[9]汪健. SoC设计的关键技术.集成电路通讯. 2006,24(1):1~10
[10]陆思安.可复用IP核以及系统芯片SOC的测试结构研究.浙江大学博士学位论文. 2003:2~3
[11]李加元,成立,王振宇,李华乐,贺星.系统芯片设计中的可复用IP技术.半导体技术. 2006,31(1):15~48
[12] M. J Y Willaims, J. B Angell. Enhancing Testability of Large-Scale Integreated Circuits via Test Points and Additional Logic. IEEE Trans. On Computers. 1973,C-22(1):46~60
[13] E. B Eichelberger, T. W Williams. A Logic Design Structure for LSITestability. Proceedings of the 14th design automation conference. New Orleans, LA, USA, 1977:462~468
[14] K. T Cheng, V. D Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Trans. On Computers. 1990,39(4):544~548
[15] IEEE Standard 1149.1-2001, IEEE Standard Test Access Port and Boundary-scan Architecture. IEEE. 2001
[16] E. J McCluskey. Built-in Self-Test Structures. IEEE Design&Test of Computers. 1985,2(2):29~36
[17]现代集成电路测试技术.化学工业出版社. 2006:16~17
[18] C. Timoc, M. Buehler, T. Griswold, C. Pina, F. Scott, L. Hess. Logical Models of Physical Failures. Proceedings of IEEE International Test Conference. Philadelphia, PA, USA, 1983:546~553
[19] J. P Roth. Diagnosis of Automata Failures: A Calculus and a Method. IBM Journal of Research and Devlopment. 1966,10(4):278~291
[20] J. P Roth, W. G Bouricius, P. R Scheider. Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEE Transactions on Electronic Computers. 1967,EC-16(10):567~580
[21] P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers. 1981,C-30(3):215~222
[22] H. Fujiwara, T. Shimono. On the Acceleration of Test Pattern Algorithms. IEEE Transactions on Computers. 1983, C-32(12):1137~1144
[23] T. M Niermann, J. H Patel. HITEC: A Test Generation Package for Sequential Circuits. Proceedings of IEEE European Design Automation Conference. Amsterdam, Netherlands, 1991:214~218
[24] H. K Lee, D. S Ha. Atalanta: an Efficient ATPG for Combinational Circuits. Technical Report. Department. of Electrical Engineer, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA, 1993:93~112
[25] I. Hamzaoglu, J. H. Patel. Test Set Compaction Algorithms for Combinational Circuits. Proceedings of IEEE International Conference on Computer-Aided Design. San Jose, CA, USA, 1998:283~289
[26] I. Hamzaoglu, J. H Patel. New Techniques for Deterministic Test PatternGeneration. Proceedings of IEEE VLSI Test Symposium. Monterey, CA, USA, 1998:446~452
[27] P. H Bardell, W. H Mcanney. Self-testing of Multiple Logic Modules. Proceedings of IEEE International Test Conference. Philadelphia, PA, USA, 1982:200~204
[28] D. Xiang, M. Chen, J. Sun, H. Fujiwara. Improving Test Effectiveness of Scan-based BIST by Scan Chain Partitioning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005, 24(6):916~927
[29]陈朝阳,张伸,沈绪榜.一种改进的SRAM并行BIST电路设计.系统工程与电子技术. 2005, 27(1):159~161
[30] C. L Nan, J. W Sying, H. F Yu. Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2006, 25(11):2586~2594
[31] C. Zoellin, H. J Wunderlich, N. Maeding, J. Leenstra. BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. IEEE International Test Conference. Santa Clara, CA, USA, 2006:1~8
[32] Y. Zorian, E. J Marinissen, S. Dey. Testing Embedded Core based System Chips. IEEE Int Test Conf. Washington DC, USA, 1998:130~143
[33] D. Bhattacharya. Hierarchical Test Acess Architecture for Embedded Cores in an Intergrated Circuit. IEEE Proc 16th VLSI Test Symp. Monterey, CA, USA, 1998:8~14
[34] I. Ghosh. N. K Jha, S. Dey. A Low Overhead Design for Testability and Test Generation Technique for Core-based Systems-on-a-chip. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 1999,18(11):1661~1676
[35] E. J Marinissen, K. Kuiper, C. Wouters. Testability and Test Protocol Expansion in Hierarchical Macro Testing. European Test Conference. Rotterdam, Netherlands, 1993:28~36
[36] P. Varma, S. Bhatia. A Structured Test Re-use Methodology for Core-based System Chips. IEEE International Test Conference. Washington DC, USA, 1998:294~302
[37] M. Benabdenbi, W. Maroufi, M. Marzouki. Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism. Proc Design, Automation and Test in European Conference and Exhibition. Munich, Germany, 2001:150~155
[38] E. J Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, C. Wouters. A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores. Proceedings of IEEE International Test Conference. Washington DC, USA, 1998:284~293
[39] IEEE P1500 General Working Group Website. IEEE P1500 Standards for Embedded Core Test [EB/OL]. http://grouper.ieee.org/groups/1500
[40]张颖,吴宁.基于SOC测试的IEEE P1500标准.电子测量技术. 2007, 30(5):119~121
[41]韩银和,胡瑜,董婕,王伟,李华伟,李晓维.数字电路测试压缩方法.信息技术快报. 2006,4(1):30-39
[42] E. M Rudnick, J. H Patel. Efficient Techniques for Dynamic Test Sequence Compaction. IEEE Transactions on Computers. 1999,48(3):323~330
[43] I. Hamzaoglu, J.H.Patel. Test Set Compaction Algorithms for Combinational Circuits. IEEE Transactions on Computer-Aided of Integrated Circuits and Systems. 2000,19(8):957~963
[44] I. Pomeranz, S. M. Reddy. Static Test Compaction for Multiple Full-scan Circuits. IEEE International Conference on Computer Design: VLSI in Computers and Processors. San Jose, CA, United States, 2003:393~396
[45]俞龙江,彭喜源,彭宇.基于蚁群算法的测试集优化.电子学报. 2003, 31(8):1178~1181
[46] A. Chandra, K. Chakrabarty. System-on-a-chip Test-data Compression and Decompression Architectures based on Golomb Codes. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2001,20(3):355~368
[47] A. Chandra, K. Chakrabarty. Test Data Compression and Decompression Based on Internal Scan Chains and Golomb Coding. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2002, 21(6):715~722
[48] A. Chandra, K. Chakrabarty. Frequency-directed Run-length Codes withApplication to System-on-a-chip Test Data Compression. Proceedings of the IEEE VLSI Test Symposium. Marina del Rey, CA, USA, 2001:42~47
[49] L. Li, K. Chakrabarty. On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression. Journal of Electronic Testing: Theory and Applications. 2004, 20(6):667~670
[50] A. H El-Maleh, R. H Al-Abaji. Extended Frequency-directed Run-length Codes with Improved Application to System-on-a-chip Test Data Compression. International Conference on Electronics, Circuits and System. Dubrovnik, Croatia, 2002:449~452
[51] Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A.Touba. An Efficient Test Vector Compression Scheme Using Selective Huffman Coding. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2003, 22(6):797~806
[52] S. Cho, J. Song, H. Yi, S. Park. Hybrid Test Data Compression Technique for SOC Scan Testing. IEEE International SOC Conference. Herndon, VA, United States, 2005:69~72
[53] P. T Gonciari, B. M Al-Hashimi, N. Nicolici. Variable-length Input Huffman Coding for System-on-a-chip Test. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2003, 22(6):783~796
[54] M. Nourani, M. Tehranipour. RL-Huffman Encoding for Test Compression and Power Reduction in Scan Applications. IEEE International Symposium on Circuits and Systems. Vancouver, BC, Canada, 2005:11681~11684
[55] Y. Doi, S. Kajihara, X. Q Wen, L. Li, K. Chakrabarty. Test Compression for Scan Circuits Using Scan Polarity Adjustment and Pinpoint Test Relaxation. Proceedings of the 2005 Conference on Asia and South Pacific Design Automation. Shanghai, China, 2005:59~64
[56] L. Lingappan, S. Ravi, A. Raghunathan, N. K Jha, S. T Chakradhar. Test Volume Reduction in Systems-on-a-chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2006,25(10):2193~2205
[57]徐磊,孙义和.关于VLSI测试数据的自适应压缩算法(SAC).中国科技论文在线. http://www.paper.edu.cn
[58]韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法.电子学报. 2004,32(8):1346~1350
[59]梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压.计算机学报. 2004,27(4):548~554
[60] F. C Wolff, C. Papachristou. Multiscan-based Test Compression and Hardware Decompression using LZ77. IEEE International Test Conference. Baltimore, MD, United States, 2002:331~339
[61] M. J Knieser, F. G Wolff, C. A Papachristou, D. J Weyer, D. R Mcintyre. A Technique for High Ratio LZW Compression. Design, Automation and Test in European Conference and Exhibition. Munich, Germany, 2003:116~121
[62] L. Li, K. Chadrabarty. Test Data Compression using Dictionaries with Fixed-length Indices. IEEE VLSI Test Symposium. Napa Valley, CA, 2003:219~224
[63] A. Wurtenberger, C. S Tautermann, S. Hellebrand. Data Compression for Multiple Scan Chains using Dictionaries with Corrections. International Test Conference. Charlotte, NC, United States, 2004:926~935
[64] M. Tehranipoor, M. Nourni, K. Chakrabarty. Nine-coded Compression Technique for Testing Embedded Cores in SoCs. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems. 2005,13(6):719~731
[65] S. P Lin, C. L Lee, J. E Chen, J. J Chen, K. L Luo, W. C Wu. A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Transactions on Very Large Scale Intergration Systems. 2007,15(7):767~776
[66] Y. Shi, N. Togawa, S. Kimura, M. Yanagisawa, T. Ohtsuki. FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction. Proceedings of the Asia and South Pacific Design Automation Conference. Yokohama, Japan, 2006: 653-658
[67] H. X Tang, S. M Reddy, I. Pomeranz. On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. IEEE International Test Conference. Charlotte, NC, United States, 2003:1079~1088
[68]于静,梁华国,蒋翠云.基于多扫描链相容压缩的距离标记压缩方法.合肥工业大学学报(自然科学版). 2006,29(1):5~9
[69]陶珏辉,梁华国,张磊.多扫描链测试集的分组标准向量压缩法.计算机辅助设计与图形学学报. 2007,19(6):686~691
[70] L. Li, K. Chakrabarty, S. Kajihara, S. Swaminathan. Efficient Space/Time Compression to Reduce Test Data Volume and Testing for IP Cores. Proceedings of the 18th International Conference on VLSI Design. Kolkata, India, 2005:53-58
[71] Q. Xu, N. Nicolici. Resource-constrained System-on-a-chip Test: a Survey. IEE Proceedings: Computers and Digital Techniques. 2005,152(1):67~81
[72] K. Omar, B. L Michael. Spectral Analysis for Statistical Response Compaction during Built-in Self-testing. Proceedings of International Test Conference. Charlotte, NC, United States, 2004:67~76
[73] T. Garbolino, M. Kopec, K. Gucwa, A. Hlawiczka. Detection, Localization and Identification of Interconnection Faults using MISR Compactor. IEEE Desing and Diagnostics of Electronic Circuits and systems. Praque, Czech Republic, 2006:228~229
[74] C. Santanu, Prashant. Zero Aliasing Space Compaction with Cellular Automata. IETE Journal of Research. 2004,50(6):425~431
[75] C. Krishnendu, H. P John. Test Response Compaction using Multiplexed Parity Trees. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 1996,15(11):1399~1408
[76]谢永乐,孙秀斌,王玉文,胡兵,陈光瑀. IP芯核测试响应的零混叠空间压缩.仪器仪表学报. 2005,26(4):395~398
[77] S. Mitra, K. S Kim. X-Compact: An Efficient Response Compaction Technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2004, 23(3):421~432
[78]韩银和.数字电路测试压缩方法研究.中国科学院研究生院博士学位论文. 2005
[79] J. Rajski, J. Tyszer, C. Wang, S. M Redd. Finite Memory Test Response Compactors for Embedded Test Applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005, 24(4):622~634
[80] Y. Han, Y. Hu, H. Li, X. Li. Theoretic Analysis and Enhanced X-Tolerance of Test Response Compact based on Convolutional Code. Proceedings ofIEEE Asia and South Pacific Design Automation Conference. Shanghai, China, 2005:53~58
[81] P. Girard. Survey of Low-power Testing of VLSI Circuits. IEEE Design and Test of Computers. 2002,19(3):82~92
[82]王伟,李晓维,张佑生,方芳.芯片测试中的功耗控制技术.第四届中国测试学术会议论文集. 2006:240~244
[83] S. Gerstendrfer, H. J Wunderlich. Minimized Power Consumption for Scan-based BIST. Journal of Electronic Testing: Theory and Applications. 2000,16(3):202~212
[84] F. Corno, P. Prinetto, M. Rebaudengo, M. S Reorda. Test Pattern Generation Methodology for Low Power Consumption. Proceedings of the IEEE VLSI Test Symposium. Monterey, CA, USA, 2004:453~457
[85] P. Girard, C. Landrault, S. Pravossoudovitch, D. Severac. Reducing Power Consumption during Test Application by Test Vector Ordering. IEEE International Symposium on Circuits and Systems. Monterey, CA, USA, 1998:296~299
[86] X. Kavousianos, D. Bakalis, M. Bellos, D. Nikolos. An Efficient Test Vector Ordering Method for Low Power Testing. Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design. Lafayette, LA, United States, 2004:285~288
[87] W. D Tseng. Scan Chain Ordering Technique for Switching Activity Reduction during Scan Test. IEE Proceedings on Computers and Digital Techniques. 2005,152(5):609~617
[88] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch. Efficient Scan Chain Design for Power Minimization during Scan Testing under Routing Constraint. IEEE International Test Conference. Charlotte, NC, United States, 2003:488~493
[89] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, A. Virazel. Design of Routing-constrained Low Power Scan Chains. Design, Automation and Test in Europe Conference and Exhibition. Paris, France, 2004:16~20
[90] X. L Huang, J. L Huang. A Routability Constrained Scan Chain Ordering Technique for Test Power Reduction. Proceedings of the Asia and SouthPacific Design Automation Conference. Yokohama, Japan, 2006:648~652
[91] A. Al-Yamani, N. Devta-Prasanna, A. Gunda. Should Illinois-Scan Based Architectures be Centralized or Distributed? IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Monterey, CA, United States, 2005:406~414
[92] P. Rosinger, B. M Al-Hashimi, N. Nicolici. Scan Architecture with Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2004, 23(7):1142~1153
[93] A. Al-Yamani, N. Devta-Prasanna, E. Chmelar, M. Grinchuk, A. Gunda. Scan Test Cost and Power Reduction through Systematic Scan Reconfiguration. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2007,26(5):907~918
[94] S. Ozgur, O. Alex. Modeling Scan Chain Modifications for Scan-in Test Power Minimization. IEEE International Test Conference. Charlotte, NC, United States, 2003:602~611
[95]李佳,胡瑜,李晓维,王伟. SCANGIN:一种降低扫描测试中动态功耗的方法.计算机辅助设计与图形学学报. 2006,18(9):1391~1396
[96] R. Sankaralingarn, B. Pouya, N. A Touba. Reducing Power Dissipation during Test using Scan Chain Disable. Proceedings of IEEE VLSI Test Symposium. Marina Del Rey, CA, 2001:319~324
[97]胡殿伟,向东.采用时钟屏蔽策略降低测试功耗.清华大学学报(自然科学版), 2007,47(7):1216~1219
[98] S. Wang, S. K Gupta. DS-LFSR: A New BIST TPG for Low Heat Dissipation. IEEE International Test Conference. Washington DC, USA, 1997:848~857
[99] F. Corno, M. Rebaudengo, M. S Reorda, G. Squillero, M. Violante. Low Power BIST via Non-Linear Hybrid Cellular Automata. Proceedings of 18th IEEE VLSI Test Symposium. Montreal, Canada, 2000:29-34
[100] K. Chakrabarty. Test Scheduleing for Core-based Systems using Mixed-integer Linear Programming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2000,19(10):1163~1174
[101] K. Chakrabarty. Optimal Test Access Architectures for System-on-a-chip.ACM Trans. Design Automation of Electronic System. 2001, 6(1):26~49
[102] E. Z Sadat, A. Ivanov. Design of an Optimal Test Access Architecture using a Genetic Algorithm. Proceedings of the Asian Test Symposium. Kyoto, 2001:205~210
[103]雷加,方刚.一种基于遗传算法的SOC测试调度方法.仪器仪表学报. 2007,28(4):15~17
[104]张永光,徐元欣,董斌,王匡.基于芯核的SOC测试调度.江南大学学报(自然科学版), 2005,4(2):129~133
[105]詹谨瑜,熊光泽.系统级芯片测试调度最优总线指定方法.计算机集成制造系统. 2006,12(10):1693~1697
[106] D. Zhao, S. J Upadhyaya. A Generic Resource Distribution and Test Scheduling Scheme for Embedded Core-Based SoCs. IEEE Transactions on Instrumentation and Measurement. 2004,53(2):318~329
[107] H. Yu, W. T Cheng, C. C Tsai, N. Mnkherjee, O. Samman, Y. Zaidan, S. M Reddy. Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design. Proceedings of the Asian Test Symposium. Kyoto, 2001:265~270
[108] Z. Wei, S. M Reddy, I. Pomeranz, H. Yu. SOC Test Scheduling using Simulated Annealing. Proceedings of IEEE VLSI Test Symposium. Napa Valley, California, 2003:325~330
[109] Y. Xia, M. Chrzanowska-Jeske, B. Wang. Core-based SOC Test Scheduling using Evolutionary Algorithm. Evolutionary Computation. IEEE/ACM International Conference on Computer-Aided Design. San Jose, CA, United States, 2003:1716~1732
[110] J. Y. Wuu, Tung-Chieh Chen, Yao-Wen Chang. SoC Test Scheduling using the B-Tree Based Floorplanning Technique. Proceedings of IEEE Asia and South Pacific Design Automation Conference. Shanghai, China, 2005:1188~1191
[111]杨军,罗岚.基于TCG图和模拟退火算法的SOC测试调度.电路与系统学报. 2006,11(5):37~43
[112] A. Chandra, K. Chakrabarty. A Unified Approach to Reduce SOC Test Data Volume, Scan Power and Testing Time. IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems. 2003,22(3):352~362
[113] D. Salomon. Data Compression: The Complete Reference. Springer-Verlag New York, Inc, New York, NY. 2000: 13~18
[114] J. Ziv, A. Lempel. A Universal Algorithm for Sequential Data Compression. IEEE Trans. on Information Theory. 1977,23(3):337~343
[115] C. J Tseng, D. P Siewiorek, Automated Synthesis of Data Paths in Digital Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1986,5(3):379~395
[116] H. Weste, K. Eshraghian. Principles of CMOS VLSI Design: A Systems Perspective. Addison Wesley Publication Company, Second Edition, 1992:48~51
[117] R. Sankaralingam, R. P Oruganti, N. A Touba. Static Compaction Techniques to Control Scan Vector Power Dissipation. IEEE VLSI Test Symposium. Montreal, Canada, 2000:35~40
[118]王伟,韩银和,胡瑜,李晓维,张佑生. SoC测试中低成本、低功耗的芯核包装方法.计算机辅助设计与图形学学报. 2006,18(9):1397~1402
[119] J. Aerts, E. J Marinissen. Scan Chain Design for Test Time Reduction in Core-based System Chips. Proceedings IEEE International Test Conference. Washington, DC, USA, 1998 :448~457
[120] I. Vikram, C. Krishnendu, J. M Erik. Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. International Test Conference. Baltimore, MD, USA, 2001:1023~1032
[121] Dan Zhao, Shambhu Upadhyaya, Dynamically Partitioned Test Scheduling With Adaptive TAM Configuration for Power-Constrained SoC Testing. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems. 2005, 24(6):956~965
[122] C. P Su, C. W Wu. A Graph-based Approach to Power Constrained SOC Test Scheduling. Journal of Electronic Testing: Theory and Applications. 2004,20(1):45~60
[123] K. Chakrabarty, V. Iyengar, M. D Krasniewski. Test Planning for Modular Testing of Hierarchical SOCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005,24(3):435~447
[124] Q. M Zhou, K. J Balakrishnan. Test Cost Reduction for SoC using a Combined Approach to Test Data Compression and Test Scheduling. Design,Automation and Test in Europe Conference and Exhibition. Nice Acropolis, France, 2007:1~6
[125]邢问训,谢金星.现代优化计算方法(第2版).清华大学出版社. 2005 :113~125
[126] X. PTang, D. F Wong. A Fast Algorithm for Block Placement based on Sequence Pair, 2001 conference on Asia South Pacific design automation, Yokohama, Japan, 2001 :521~526
[127] Y. Huang, S. M Reddy, W. T Cheng, P. Reuter, N. Mukherjee, C. C Tsai, O. Samman, Y. Zaidan. Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. IEEE International Test Conference. Baltimore, MD, USA, 2002:74~82
[128] V. Iyengar, K. Chakrabarty, E. J Marinissen. Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Tran. On Computers. 2003,52(12):1619~1632
[129] Y. Xia, M. C Jeske, B. Wang, M. Jeske, Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. IEEE/ACM International Conference on Computer-Aided Design. San Jose, CA, United States, 2003:100~105
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