VLSI受工艺参数扰动影响的若干问题研究
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摘要
作为有史以来发展最为迅速的工业之一,半导体工业的进步使大规模集成电路的特征尺寸不断缩小、芯片集成度不断提高。如今,半导体芯片的规模已达到数亿晶体管,原来需要多个芯片共同实现的电子系统也已可以完成单片集成,这不仅使器件和电路的性能得到了提高,同时也使单位电路功能的生产成本得以下降。但是,随着器件的最小尺寸进入65nm层级,一系列复杂工艺和新材料的应用将带来随机的工艺参数扰动。这些工艺参数扰动会直接造成集成电路的关键几何尺寸及电学参数与设计标称值之间产生严重偏差,从而导致芯片性能不可预测,大大增加了集成电路的设计难度,降低了集成电路的成品率
针对该情况,本文着重研究了超大规模集成电路中工艺参数扰动的问题,分别从耦合互连线传输性能分析、芯片参数成品率估计与多目标优化以及电路标称值设计优化三方面入手,依次以电路级、芯片级、系统级的角度探讨了工艺参数扰动对集成电路性能的影响。其主要的研究工作有：
第一,对于均匀耦合互连线模型,利用频域方法针对互连线集总电路进行分析。该方法首先将耦合互连线模型在线元分析阶段进行复频域去耦,使原本复杂的耦合互连线模型转化为独立互连线模型。然后,利用两条独立互连线的瞬态响应关系给出了串扰噪声的时域仿真表达式,并通过实验验证了其在串扰仿真评估中的有效性。另外,考虑实际电路中激励信号不理想对耦合互连线时延分析的影响,还建立了斜阶跃信号激励下的互连线时延模型,提出了基于耦合RLC互连线集总模型的时延分析方法。对于去耦后的耦合互连线模型,该方法利用二阶矩模型及改进的一阶模型对其传递函数进行化简,并通过数值方法给出了简洁的耦合互连线时延估计表达式。实验结果表明该方法可以对斜阶跃信号激励下的均匀耦合RLC互连线时延进行有效评估。
第二,针对工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的耦合互连线双线随机模型,提出了基于随机谱方法的互连线串扰噪声和互连时延估计方法。该方法通过主成分分析理论对工艺参数扰动的强相关性进行去耦,分别利用两种随机谱方法(随机伽辽金方法和随机点匹配方法)与多项式混沌展开相结合,对耦合互连线的串扰噪声及互连时延进行估计。然后,通过复逼近及数值计算方法给出了工艺参数扰动下耦合RLC互连线串扰及时延估计的有限维表达式。此外,考虑多根互连线间的寄生耦合效应,还建立了多互连线耦合的RLC随机模型。根据该模型的求解规模,采用有效的随机谱方法对多耦合互连线的互连时延进行分析,最终利用数值方法推导出了相应的互连时延时域表达式。
第三,考虑工艺参数扰动对大规模集成电路参数成品率估计的影响,提出了基于切比雪夫仿射技术的参数成品率估计方法。该方法针对通常工艺参数相关性未知的情况,利用仿射技术得到了漏电功耗及芯片时延的CDF上下边界,并通过此分布边界估计了漏电功耗成品率和芯片时延成品率。随后,在该参数成品率估计方法的基础上,又提出了基于自适应加权求和的成品率多目标优化方法。这种优化方法同时将相互制约的漏电功耗成品率及芯片时延成品率作为优化目标建立了功耗-时延优化模型,并通过自适应加权求和方法对该模型进行细化求解,以达到功耗成品率及时延成品率的均衡优化,从而得到了一组分布均匀的帕雷托优化解。实验结果表明,该方法可以有效的解决传统优化方法在帕雷托曲线变化率较小的地方求解不到优化解的问题,使设计者可以根据对漏电功耗成品率及芯片时延成品率的不同要求弹性的选择最佳优化解。
最后,考虑工艺参数扰动概率分布的不确定性,提出了一种同时考虑参数域及性能域设计参数的鲁棒性量化方法。该方法从输出端性能限制条件入手,根据后向映射及前向映射方法定义设计空间及性能空间的可接受域作为设计参数的鲁棒性指标,并利用基于范数距离的度量方法对工艺参数扰动下的设计参数及性能波动进行了鲁棒性量化。随后,在该鲁棒性量化方法的基础上,又提出了一种基于替代模型管理框架的集成电路鲁棒性优化方法。该方法同时考虑具有相互制约特性的参数鲁棒性及性能鲁棒性建立集成电路鲁棒性的双目标优化模型,并利用替代函数使集成电路的鲁棒性在参数域及性能域内达到均衡优化。
As one of the fastest developing industries, the improvement of semiconductor industry makes it possible to produce VLSI devices with continuous decreasing feature sizes and increasing integration. Nowadays, as many as billions of transistors can be integrated in a single semiconductor chip. The electronic system, used to be implemented by several chips before, can be manufactured by using monolithic integration. This advantage not only improves the performance of devices and circuits, but also decreases the cost of circuit function unit. However as device feature size shrinks to below 65nm, the application of complex technologies and new materials will inevitably introduce stochastic process variations. These process variations directly induce significant deviation between the key geometric sizes, electrical parameters and their nominal design values, and further lead to the unpredictability of chip performance, increasing difficulty of VLSI design and degradation of circuit yield.
To address this issue, this dissertation concentrates on the problem of process variations in VLSI circuits, and researches the impact of process variations at circuit level, chip level and system level respectively. In accordance, three aspects of problems are conducted in this research:the transmission line performance analysis, parameter yield estimation and multi-objective yield optimization, and circuit nominal design optimization. The main research points in this dissertation can be summarized as follows:
Firstly, based on the uniform coupled interconnects model, the lumped circuit for interconnects is analyzed by the application of frequency domain method. This method decouples the coupled interconnect model in complex frequency domain and transforms the coupled model into independent interconnects. Then in time domain the estimated expression of crosstalk noise in uniform RLC model is presented, according to the transient response functions of the transformed independent interconnects. The effectiveness of the estimated expression is verified by experimental results. Moreover, the excitation signal in actual circuits is always non-ideal, which has a predominant impact on the analysis of interconnect delay. Considering this impact, an analytical delay model based on coupled RLC interconnect model is presented. For the decoupled interconnects, the two-pole model is combined with the modified one-pole model to simplify the transfer function. The delay expression for coupled interconnects is further proposed by numerical method. Experimental results demonstrate that the analytical method is capable of estimating the delay in coupled RLC interconnects effectively.
Secondly, process variations also have an impact on the performance of interconnects. To evaluate this impact, a spectral stochastic method based analysis method for interconnect crosstalk and delay is presented. The suggested method decouples the strongly correlated process variations into orthogonal random variables by principle component analysis. By employing polynomial chaos expression, this work applies two spectral methods, stochastic galerkin method and stochastic collocation method, to estimate the crosstalk and delay in coupled transmission lines. A finite representation of interconnect crosstalk and delay can be further obtained by complex approximation method and numerical method. Furthermore, considering the parasitic coupling effect of multi-interconnects, the stochastic model for multi-interconnects is established. Based on this stochastic model, the delay is estimated by spectrum domain stochastic method and the delay expression in time domain can be finally derived.
Thirdly, considering the impact of process variations on VLSI parameter yield, a chebyshev affine arithmetic based yield estimation approach is proposed. Under the assumption of unknown relationships among process variations, this technique predicts the CDF (Cumulative Distribution Function) bounds for leakage power and circuit delay respectively, and estimates the leakage power yield and circuit delay yield based on the predicted distributions. Then by using this estimation technique for parametric yield, a yield multi-objective optimization framework is proposed based on the adaptive weighted sum method. This optimization framework regards both timing and power yield as objective functions and solves the power-delay multi-objective optimization problem with AWS method. AWS is helpful in obtaining a set of uniformly distributed pareto-optimal solutions, therefore is capable of providing sufficient trade-off information between power and delay yield. Experimental results demonstrate that the proposed multi-objective framework effectively solves the problem in traditional optimization methods that optimal solution cannot be obtained in the regions where the curvature of pareto surface is insignificant. Consequently the designer can choose the optimal solutions with different emphasis points.
Finally, considering the uncertain distribution of process variations, a robustness quantification rmethod for design parameters in both parameter space and performance space is proposed. Starting with the performance constraints in performance space, this proposed technique applies backward mapping and forward mapping to explore the feasible regions in parameter space and performance space respectively, for the purpose of quantifying the robustness of design parameters in both parameter space and performance space. The robustness indexes are computed based on norm distances. Then with the robustness indexes quantified by this new methodology, a design optimization procedure based on surrogate management framework is proposed. Both parameter robustness and performance robustness are taken into account to construct a bi-objective model and find the trade-off between these two robustness metrics by the surrogates.
针对该情况,本文着重研究了超大规模集成电路中工艺参数扰动的问题,分别从耦合互连线传输性能分析、芯片参数成品率估计与多目标优化以及电路标称值设计优化三方面入手,依次以电路级、芯片级、系统级的角度探讨了工艺参数扰动对集成电路性能的影响。其主要的研究工作有：
第一,对于均匀耦合互连线模型,利用频域方法针对互连线集总电路进行分析。该方法首先将耦合互连线模型在线元分析阶段进行复频域去耦,使原本复杂的耦合互连线模型转化为独立互连线模型。然后,利用两条独立互连线的瞬态响应关系给出了串扰噪声的时域仿真表达式,并通过实验验证了其在串扰仿真评估中的有效性。另外,考虑实际电路中激励信号不理想对耦合互连线时延分析的影响,还建立了斜阶跃信号激励下的互连线时延模型,提出了基于耦合RLC互连线集总模型的时延分析方法。对于去耦后的耦合互连线模型,该方法利用二阶矩模型及改进的一阶模型对其传递函数进行化简,并通过数值方法给出了简洁的耦合互连线时延估计表达式。实验结果表明该方法可以对斜阶跃信号激励下的均匀耦合RLC互连线时延进行有效评估。
第二,针对工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的耦合互连线双线随机模型,提出了基于随机谱方法的互连线串扰噪声和互连时延估计方法。该方法通过主成分分析理论对工艺参数扰动的强相关性进行去耦,分别利用两种随机谱方法(随机伽辽金方法和随机点匹配方法)与多项式混沌展开相结合,对耦合互连线的串扰噪声及互连时延进行估计。然后,通过复逼近及数值计算方法给出了工艺参数扰动下耦合RLC互连线串扰及时延估计的有限维表达式。此外,考虑多根互连线间的寄生耦合效应,还建立了多互连线耦合的RLC随机模型。根据该模型的求解规模,采用有效的随机谱方法对多耦合互连线的互连时延进行分析,最终利用数值方法推导出了相应的互连时延时域表达式。
第三,考虑工艺参数扰动对大规模集成电路参数成品率估计的影响,提出了基于切比雪夫仿射技术的参数成品率估计方法。该方法针对通常工艺参数相关性未知的情况,利用仿射技术得到了漏电功耗及芯片时延的CDF上下边界,并通过此分布边界估计了漏电功耗成品率和芯片时延成品率。随后,在该参数成品率估计方法的基础上,又提出了基于自适应加权求和的成品率多目标优化方法。这种优化方法同时将相互制约的漏电功耗成品率及芯片时延成品率作为优化目标建立了功耗-时延优化模型,并通过自适应加权求和方法对该模型进行细化求解,以达到功耗成品率及时延成品率的均衡优化,从而得到了一组分布均匀的帕雷托优化解。实验结果表明,该方法可以有效的解决传统优化方法在帕雷托曲线变化率较小的地方求解不到优化解的问题,使设计者可以根据对漏电功耗成品率及芯片时延成品率的不同要求弹性的选择最佳优化解。
最后,考虑工艺参数扰动概率分布的不确定性,提出了一种同时考虑参数域及性能域设计参数的鲁棒性量化方法。该方法从输出端性能限制条件入手,根据后向映射及前向映射方法定义设计空间及性能空间的可接受域作为设计参数的鲁棒性指标,并利用基于范数距离的度量方法对工艺参数扰动下的设计参数及性能波动进行了鲁棒性量化。随后,在该鲁棒性量化方法的基础上,又提出了一种基于替代模型管理框架的集成电路鲁棒性优化方法。该方法同时考虑具有相互制约特性的参数鲁棒性及性能鲁棒性建立集成电路鲁棒性的双目标优化模型,并利用替代函数使集成电路的鲁棒性在参数域及性能域内达到均衡优化。
As one of the fastest developing industries, the improvement of semiconductor industry makes it possible to produce VLSI devices with continuous decreasing feature sizes and increasing integration. Nowadays, as many as billions of transistors can be integrated in a single semiconductor chip. The electronic system, used to be implemented by several chips before, can be manufactured by using monolithic integration. This advantage not only improves the performance of devices and circuits, but also decreases the cost of circuit function unit. However as device feature size shrinks to below 65nm, the application of complex technologies and new materials will inevitably introduce stochastic process variations. These process variations directly induce significant deviation between the key geometric sizes, electrical parameters and their nominal design values, and further lead to the unpredictability of chip performance, increasing difficulty of VLSI design and degradation of circuit yield.
To address this issue, this dissertation concentrates on the problem of process variations in VLSI circuits, and researches the impact of process variations at circuit level, chip level and system level respectively. In accordance, three aspects of problems are conducted in this research:the transmission line performance analysis, parameter yield estimation and multi-objective yield optimization, and circuit nominal design optimization. The main research points in this dissertation can be summarized as follows:
Firstly, based on the uniform coupled interconnects model, the lumped circuit for interconnects is analyzed by the application of frequency domain method. This method decouples the coupled interconnect model in complex frequency domain and transforms the coupled model into independent interconnects. Then in time domain the estimated expression of crosstalk noise in uniform RLC model is presented, according to the transient response functions of the transformed independent interconnects. The effectiveness of the estimated expression is verified by experimental results. Moreover, the excitation signal in actual circuits is always non-ideal, which has a predominant impact on the analysis of interconnect delay. Considering this impact, an analytical delay model based on coupled RLC interconnect model is presented. For the decoupled interconnects, the two-pole model is combined with the modified one-pole model to simplify the transfer function. The delay expression for coupled interconnects is further proposed by numerical method. Experimental results demonstrate that the analytical method is capable of estimating the delay in coupled RLC interconnects effectively.
Secondly, process variations also have an impact on the performance of interconnects. To evaluate this impact, a spectral stochastic method based analysis method for interconnect crosstalk and delay is presented. The suggested method decouples the strongly correlated process variations into orthogonal random variables by principle component analysis. By employing polynomial chaos expression, this work applies two spectral methods, stochastic galerkin method and stochastic collocation method, to estimate the crosstalk and delay in coupled transmission lines. A finite representation of interconnect crosstalk and delay can be further obtained by complex approximation method and numerical method. Furthermore, considering the parasitic coupling effect of multi-interconnects, the stochastic model for multi-interconnects is established. Based on this stochastic model, the delay is estimated by spectrum domain stochastic method and the delay expression in time domain can be finally derived.
Thirdly, considering the impact of process variations on VLSI parameter yield, a chebyshev affine arithmetic based yield estimation approach is proposed. Under the assumption of unknown relationships among process variations, this technique predicts the CDF (Cumulative Distribution Function) bounds for leakage power and circuit delay respectively, and estimates the leakage power yield and circuit delay yield based on the predicted distributions. Then by using this estimation technique for parametric yield, a yield multi-objective optimization framework is proposed based on the adaptive weighted sum method. This optimization framework regards both timing and power yield as objective functions and solves the power-delay multi-objective optimization problem with AWS method. AWS is helpful in obtaining a set of uniformly distributed pareto-optimal solutions, therefore is capable of providing sufficient trade-off information between power and delay yield. Experimental results demonstrate that the proposed multi-objective framework effectively solves the problem in traditional optimization methods that optimal solution cannot be obtained in the regions where the curvature of pareto surface is insignificant. Consequently the designer can choose the optimal solutions with different emphasis points.
Finally, considering the uncertain distribution of process variations, a robustness quantification rmethod for design parameters in both parameter space and performance space is proposed. Starting with the performance constraints in performance space, this proposed technique applies backward mapping and forward mapping to explore the feasible regions in parameter space and performance space respectively, for the purpose of quantifying the robustness of design parameters in both parameter space and performance space. The robustness indexes are computed based on norm distances. Then with the robustness indexes quantified by this new methodology, a design optimization procedure based on surrogate management framework is proposed. Both parameter robustness and performance robustness are taken into account to construct a bi-objective model and find the trade-off between these two robustness metrics by the surrogates.
引文
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