三阶Delta-Sigma调制器的设计
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摘要
随着便携式电子设备对低功耗高分辨率的模数转换器的需求越来越人,Sigma-Delta模数转换器以其能够以较低的成本取得极高的分辨率,在多种应用领域获得了广泛的应用,尤其在例如测量类和音频类ADC的应用中,对于模数转换的低速高精度要求使得Delta-SigmaADC结构成为首选。
论文主要针对Sigma-Delta模数转换器的模拟部分即Sigma-Delta调制器进行研究设计。根据自顶向下的设计理念,从系统结构的选择、系统建模到电路实现完成了整个调制器的设计。Sigma-Delta调制器通常包含的模拟电路比较简单,对电路精度的依赖性较低,因此在电路设计上比较宽裕,本文更加注重其系统的设计。
针对系统结构的选择,本文首先比较了单位量化器、多位量化器,一阶、多阶,单环、级联,前馈、反馈,离散时间、连续时间等不同类型∑-△ADC的优缺点,初步确定了设计所采用的调制器结构类型,再针对该类型提出3个不同方案分别进行仿真比较得到所需的系统参数。最后就两种不同积分器构成系统框图所需的时序进行可行性分析,进一步确定了系统结构。系统采用包含场谐振器的单环前馈(CRFF)3阶一位量化器结构。
针对系统建模,论文引入了线性模型、quasi线性模型和主要应用与系统稳定性分析的非线性模型。实际电路包含着诸如运放增益有限性、运放带宽有限性、开关导通电阻、时钟抖动、时钟馈通、电荷注入等非理想性。本文通过具体分析在线性模型下对这些非理想性建模得到更加完善的模型。
针对电路实现,主要的电路模块运放和比较器分别采用了电流镜结构AB类输出的运放和离散时间比较器。设计的运放在符合系统指标的前提下同时具有高增益带宽积低功耗高输出摆幅的特点,而离散时间比较器具有高精度低功耗的优点。运放的开关共模反馈电路和离散时间比较器与整体系统采用开关电容结构有很好的兼容性。
整体电路使用TSMC 0.35μm混合信号CMOS工艺,采用Spectre进行仿真。仿真表明,在信号输入带宽为1kHz,超采样率为128条件下,调制器的动态输入范围为102dB;在信号为-3.5dB满幅输入时,其最大信号/噪声失真比为97.84dB;此外,在1.5V供电电压下,调制器的功耗仅为88μW,表现出较好的低功耗高精度性能。
As the mobile electrical device pay more and more attention to the low power analog to digital converter of high definition,Sigma-Delta analog digital converter (ADC) is wildly used in many fields because it can achieve very high definition while maintain the low cost and become the first choice especially in the measurement and audio application.
A Sigma-Delta ADC designed by the top-down design idea is presented in this paper. The structure is chosen at first,then a linear model is given according to the structure and the circuit is implemented with the parameters simulated from the model. The circuit design is relatively relax because of the low requirement of the analog circuit and circuit precision.So more attention is paid to the design of the system level.
Many different pair types of Sigma-Delta modulator such as single bit and multi-bit,first order and high order,single loop and MASM,feedforward and feedback, switched-capacitor and continuous time et,is proposed and compared to make a decision which structure is most suitable for the given specification.Then three topologies is simulated based on the decided structure.Finally a three order chain of integrator with field resonator and single bit quantizer single loop structure is chosen for this design.And the system structure is furthermore determined when the structure timing is checked for realization.
Linear model,quasi linear model is introduced in this paper for the modeling of the system.And non-linear model which is especial applied in stability analyzing is also presented in this paper.Circuit nonlinearities,such as finite dc gain of opamp,finite bandwidth of opamp,switch turn on resistance,clock jitter, clock feed-through,charge injection et,is analyzed based on linear model and added as noise.Then an improved model is finally constructed.
For the circuit implementation a current mirror class AB opamp is designed in the integrator.It has a better performance of gain bandwidth,power dissipation and output swing under the given specification.And a regenerative comparator is choose for the quantizer as its high resolution and low power dissipation.Both of them have the advantage in the compatibility of switched-capacitor circuits.
Simulation using Spectre is based on the TSMC 0.35μm mixed signal CMOS process. The results show the modulator achieves a simulated dynamic-range(DR) of 102-dB and a peak signal-to-noise-and-distortion-ratio(SNDR) of 97.84-dB @ -3.5dBFS in a 1-kHz signal bandwidth with an oversampling ratio(OSR) of 128.The power dissipation of the modulator is only 88-μW under 1.5-V supply voltage,indicating low power and high resolution.
论文主要针对Sigma-Delta模数转换器的模拟部分即Sigma-Delta调制器进行研究设计。根据自顶向下的设计理念,从系统结构的选择、系统建模到电路实现完成了整个调制器的设计。Sigma-Delta调制器通常包含的模拟电路比较简单,对电路精度的依赖性较低,因此在电路设计上比较宽裕,本文更加注重其系统的设计。
针对系统结构的选择,本文首先比较了单位量化器、多位量化器,一阶、多阶,单环、级联,前馈、反馈,离散时间、连续时间等不同类型∑-△ADC的优缺点,初步确定了设计所采用的调制器结构类型,再针对该类型提出3个不同方案分别进行仿真比较得到所需的系统参数。最后就两种不同积分器构成系统框图所需的时序进行可行性分析,进一步确定了系统结构。系统采用包含场谐振器的单环前馈(CRFF)3阶一位量化器结构。
针对系统建模,论文引入了线性模型、quasi线性模型和主要应用与系统稳定性分析的非线性模型。实际电路包含着诸如运放增益有限性、运放带宽有限性、开关导通电阻、时钟抖动、时钟馈通、电荷注入等非理想性。本文通过具体分析在线性模型下对这些非理想性建模得到更加完善的模型。
针对电路实现,主要的电路模块运放和比较器分别采用了电流镜结构AB类输出的运放和离散时间比较器。设计的运放在符合系统指标的前提下同时具有高增益带宽积低功耗高输出摆幅的特点,而离散时间比较器具有高精度低功耗的优点。运放的开关共模反馈电路和离散时间比较器与整体系统采用开关电容结构有很好的兼容性。
整体电路使用TSMC 0.35μm混合信号CMOS工艺,采用Spectre进行仿真。仿真表明,在信号输入带宽为1kHz,超采样率为128条件下,调制器的动态输入范围为102dB;在信号为-3.5dB满幅输入时,其最大信号/噪声失真比为97.84dB;此外,在1.5V供电电压下,调制器的功耗仅为88μW,表现出较好的低功耗高精度性能。
As the mobile electrical device pay more and more attention to the low power analog to digital converter of high definition,Sigma-Delta analog digital converter (ADC) is wildly used in many fields because it can achieve very high definition while maintain the low cost and become the first choice especially in the measurement and audio application.
A Sigma-Delta ADC designed by the top-down design idea is presented in this paper. The structure is chosen at first,then a linear model is given according to the structure and the circuit is implemented with the parameters simulated from the model. The circuit design is relatively relax because of the low requirement of the analog circuit and circuit precision.So more attention is paid to the design of the system level.
Many different pair types of Sigma-Delta modulator such as single bit and multi-bit,first order and high order,single loop and MASM,feedforward and feedback, switched-capacitor and continuous time et,is proposed and compared to make a decision which structure is most suitable for the given specification.Then three topologies is simulated based on the decided structure.Finally a three order chain of integrator with field resonator and single bit quantizer single loop structure is chosen for this design.And the system structure is furthermore determined when the structure timing is checked for realization.
Linear model,quasi linear model is introduced in this paper for the modeling of the system.And non-linear model which is especial applied in stability analyzing is also presented in this paper.Circuit nonlinearities,such as finite dc gain of opamp,finite bandwidth of opamp,switch turn on resistance,clock jitter, clock feed-through,charge injection et,is analyzed based on linear model and added as noise.Then an improved model is finally constructed.
For the circuit implementation a current mirror class AB opamp is designed in the integrator.It has a better performance of gain bandwidth,power dissipation and output swing under the given specification.And a regenerative comparator is choose for the quantizer as its high resolution and low power dissipation.Both of them have the advantage in the compatibility of switched-capacitor circuits.
Simulation using Spectre is based on the TSMC 0.35μm mixed signal CMOS process. The results show the modulator achieves a simulated dynamic-range(DR) of 102-dB and a peak signal-to-noise-and-distortion-ratio(SNDR) of 97.84-dB @ -3.5dBFS in a 1-kHz signal bandwidth with an oversampling ratio(OSR) of 128.The power dissipation of the modulator is only 88-μW under 1.5-V supply voltage,indicating low power and high resolution.
引文
[1]PELUSO,V.,STEYAERT,M.,SANSEN,W.,"Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters," Kluwer Academic Publishers,Boston,1999.
[2]S.K.Gupta and V.Fong,"A 64-MHz clock-rate ADC with 88-dB SNDR and105-dB IM3 distortion at a 1.5-MHz signal frequency," IEEE J.Solid-State Circuits,vol.37,pp.1653-1661,Dec.2002.
[3]SCHREIER R and TEMES G C.Understanding Delta-Sigma Data Converters[M].Piscataway,NJ:IEEE Press,2005.
[4]RABII,S.and WOOLEY,B.A.,"The Design of Low-Voltage,Low-Power Sigma-Delta Modulators," Kluwer Academic Publishers,1999.
[5]Sean Chuang,Xianggang Yu,Terry L.Sculley,and Roberto H.Bamberger,"Design and Implementation of a Sixth Order Bandpass Delta-Sigma A/D Converter with Single Quantizer," IEEE ISCS,Hong Kong,June 9-12,1997.
[6]S.A.Jantzi,W.M.Snelgrove,P.F.Ferguson,"A Fourth-Order Bandpass Sigma-Delta Modulator," IEEE J.Solid-state Circuits,pp.282-291,vol.28,no.3,Mar.1993.
[7]John K.Fiorenza,Todd Sepke,and Peter Holloway,et al,"Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies," IEEE J.Solid-State Circuits,vol.41,N0.12,Dec.2006.
[8]D.A.Johns and K.Martin,Analog Integrated Circuit Design,John Wiley & Sons,New York,1997,pp.450-451.
[9]A.Oppenheim and R.Schafer,Discrete-Time Signal Processing,Prentice-Hall,1989.
[10]B.Razavi,Principles of Data Conversion System Design,IEEE Press,1995.
[11]J.Candy and G.Temes,"Oversampling methods for A/D and D/A conversion,"in Oversampling Delta-Sigma Data Converters,pp.1-25,IEEE Press,1992.
[12]B.Leung,"Theory of sigma-delta analog to digital converter," IEEE International Symposium on Circuits and Systems Tutorials,pp.196-223,1994.
[13]CANDY,J.C.,"Decimation for Sigma Delta Modulation," IEEE Transaction on Communication,COM-34(1):72-76,1986.
[14]Shahriar Rabii and Bruce A.Wooley,"The Design of Low-Voltage Low-Power Sigma-Delta Modulators," Kluwer Academic Publishers,Boston,1999.
[15]Pervez M.Aziz,Henrik V.Sorensen,and Jan Van Der Spiegel,"An Overview of Sigma-Delta Converters," IEEE Signal Processing Magazine,pp:61-84,1996.
[16]17.S.Norsworthy and D.Rich,"Idle channel tones and dithering in delta sigma modulators," 95thConvention of the Audioengineering Society,pre-print 3711,October,1993.
[17]M.Sarhang-Nejad and G.Temes,"A high-resolution multibit Sigma-Delta ADC with digital correction and relaxed amplifier requirements," IEEE Journal of Solid State Circuits,pp.648-660,June,1993.
[18]R.Gray,"Quantization Noise Spectra," Oversampled Delta-Sigma Data Converters Short Course Portland,Oregon,June 1992.
[19]W.L.Lee,"A novel higher order interpolative modulator topology for high resolution oversampling A/D converters," Master' s Thesis,Massachusetts Institute of Technology,Cambridge,MA.June 1987.
[20]K.C.H.Chao,S.Nadeem,W.L.Lee,and C.G.Sodini,"A higher order topology for interpolative modulators for oversampling A/D conversion," IEEE Transaction on Circuits and Systems,vol 37,pp.309-318,March 1990.
[21]S.Norsworthy,I.Post,H.Fetterman,"A 14-bit 80kHz sigma-delta A/Dconverter:modeling,design,and performance evaluation," IEEE Joumal of Solid State Circuits,pp.256-266,April,1989.
[22]S.Ardalan and J.Paulos,"An analysis of nonlinear behavior in delta-sigma modulators," IEEE Transactions on Circuits and Systems,pp.593-603,June,1987.
[23]Philip Steiner and Woodward Yang,"Stability of high order sigma-delta modulators," IEEE Magzines,pp 52-55.1996.
[24]X.Weize and E.G.Friedman,"Clock-feedthrough in CMOS analog transmission gate switches," in Annu.IEEE Int.ASIC/SOC Conf.,Sep.2002,pp.181-185.
[25]YAO L,STEYEART M S J,and SANSEN W," A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS," IEEE J.Solid-State Circuits,Nov.1998,vol.39,no.11,pp.1809-1818
[26]CHOKSI O,and CARLEY L R,"Analysis of Switched-Capacitor Common-Mode Feedback Circuit," IEEE Trans.CircuitsSysL Ⅱ.Dec 2003,vol.50,no.12,pp.906-917.
[27]SAMID L,VOLZ P,and MANOLI Y," A Dynamic Analysis of A Latched CMOS Comparator," ISCAS 2004.
[28]PELUSO,V.,VANCORENLAND,P.,MARQUES,A.M.,STEYAERT,M.,SANSEN,W.,"A 900-mV Low-Power Σ△ A/D Converter with 77-dB Dynamic Range," IEEE Journal of Solid-State Circuits,Vol.33,No.12,pp.1887-1897,1998.
[29]GOES J,VAZB,and MONTEIRO R,et al." A 0.9 V △ Σ modulator with 80 dB SNDR and 83 dB DR using a single-phase technique," IEEE ISSCC Dig.Tech.Papers,2006,pp.74-75.
[30]ROH J,BYUN S,and CHOI Y,et al."A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range," IEEE J.Solid-State Circuits,Feb.2008,vol.43,no.2,pp.361-370.
[2]S.K.Gupta and V.Fong,"A 64-MHz clock-rate ADC with 88-dB SNDR and105-dB IM3 distortion at a 1.5-MHz signal frequency," IEEE J.Solid-State Circuits,vol.37,pp.1653-1661,Dec.2002.
[3]SCHREIER R and TEMES G C.Understanding Delta-Sigma Data Converters[M].Piscataway,NJ:IEEE Press,2005.
[4]RABII,S.and WOOLEY,B.A.,"The Design of Low-Voltage,Low-Power Sigma-Delta Modulators," Kluwer Academic Publishers,1999.
[5]Sean Chuang,Xianggang Yu,Terry L.Sculley,and Roberto H.Bamberger,"Design and Implementation of a Sixth Order Bandpass Delta-Sigma A/D Converter with Single Quantizer," IEEE ISCS,Hong Kong,June 9-12,1997.
[6]S.A.Jantzi,W.M.Snelgrove,P.F.Ferguson,"A Fourth-Order Bandpass Sigma-Delta Modulator," IEEE J.Solid-state Circuits,pp.282-291,vol.28,no.3,Mar.1993.
[7]John K.Fiorenza,Todd Sepke,and Peter Holloway,et al,"Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies," IEEE J.Solid-State Circuits,vol.41,N0.12,Dec.2006.
[8]D.A.Johns and K.Martin,Analog Integrated Circuit Design,John Wiley & Sons,New York,1997,pp.450-451.
[9]A.Oppenheim and R.Schafer,Discrete-Time Signal Processing,Prentice-Hall,1989.
[10]B.Razavi,Principles of Data Conversion System Design,IEEE Press,1995.
[11]J.Candy and G.Temes,"Oversampling methods for A/D and D/A conversion,"in Oversampling Delta-Sigma Data Converters,pp.1-25,IEEE Press,1992.
[12]B.Leung,"Theory of sigma-delta analog to digital converter," IEEE International Symposium on Circuits and Systems Tutorials,pp.196-223,1994.
[13]CANDY,J.C.,"Decimation for Sigma Delta Modulation," IEEE Transaction on Communication,COM-34(1):72-76,1986.
[14]Shahriar Rabii and Bruce A.Wooley,"The Design of Low-Voltage Low-Power Sigma-Delta Modulators," Kluwer Academic Publishers,Boston,1999.
[15]Pervez M.Aziz,Henrik V.Sorensen,and Jan Van Der Spiegel,"An Overview of Sigma-Delta Converters," IEEE Signal Processing Magazine,pp:61-84,1996.
[16]17.S.Norsworthy and D.Rich,"Idle channel tones and dithering in delta sigma modulators," 95thConvention of the Audioengineering Society,pre-print 3711,October,1993.
[17]M.Sarhang-Nejad and G.Temes,"A high-resolution multibit Sigma-Delta ADC with digital correction and relaxed amplifier requirements," IEEE Journal of Solid State Circuits,pp.648-660,June,1993.
[18]R.Gray,"Quantization Noise Spectra," Oversampled Delta-Sigma Data Converters Short Course Portland,Oregon,June 1992.
[19]W.L.Lee,"A novel higher order interpolative modulator topology for high resolution oversampling A/D converters," Master' s Thesis,Massachusetts Institute of Technology,Cambridge,MA.June 1987.
[20]K.C.H.Chao,S.Nadeem,W.L.Lee,and C.G.Sodini,"A higher order topology for interpolative modulators for oversampling A/D conversion," IEEE Transaction on Circuits and Systems,vol 37,pp.309-318,March 1990.
[21]S.Norsworthy,I.Post,H.Fetterman,"A 14-bit 80kHz sigma-delta A/Dconverter:modeling,design,and performance evaluation," IEEE Joumal of Solid State Circuits,pp.256-266,April,1989.
[22]S.Ardalan and J.Paulos,"An analysis of nonlinear behavior in delta-sigma modulators," IEEE Transactions on Circuits and Systems,pp.593-603,June,1987.
[23]Philip Steiner and Woodward Yang,"Stability of high order sigma-delta modulators," IEEE Magzines,pp 52-55.1996.
[24]X.Weize and E.G.Friedman,"Clock-feedthrough in CMOS analog transmission gate switches," in Annu.IEEE Int.ASIC/SOC Conf.,Sep.2002,pp.181-185.
[25]YAO L,STEYEART M S J,and SANSEN W," A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS," IEEE J.Solid-State Circuits,Nov.1998,vol.39,no.11,pp.1809-1818
[26]CHOKSI O,and CARLEY L R,"Analysis of Switched-Capacitor Common-Mode Feedback Circuit," IEEE Trans.CircuitsSysL Ⅱ.Dec 2003,vol.50,no.12,pp.906-917.
[27]SAMID L,VOLZ P,and MANOLI Y," A Dynamic Analysis of A Latched CMOS Comparator," ISCAS 2004.
[28]PELUSO,V.,VANCORENLAND,P.,MARQUES,A.M.,STEYAERT,M.,SANSEN,W.,"A 900-mV Low-Power Σ△ A/D Converter with 77-dB Dynamic Range," IEEE Journal of Solid-State Circuits,Vol.33,No.12,pp.1887-1897,1998.
[29]GOES J,VAZB,and MONTEIRO R,et al." A 0.9 V △ Σ modulator with 80 dB SNDR and 83 dB DR using a single-phase technique," IEEE ISSCC Dig.Tech.Papers,2006,pp.74-75.
[30]ROH J,BYUN S,and CHOI Y,et al."A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range," IEEE J.Solid-State Circuits,Feb.2008,vol.43,no.2,pp.361-370.