基于ARM的H.264 & AVS联合解码器的ESL建模
摘要
随着90nm技术的出现,上亿门规模电路的开发及系统的复杂度俱增,嵌入式软件开发任务与系统架构设计工作量的增加远大于硬件实现复杂度的增加,设计前期在系统级别进行软硬件划分、提早的进行软件开发成为一款SoC芯片成功的关键因素。目前的RTL级别的设计方法软硬件协同仿真在整个设计周期的中后期才开始进行,不利于尽早发现设计中的瓶颈与提前开始软件的开发。先进的视频解码SoC系统需要在设计前期在系统级别进行软硬件规划,同时迫切需要高效的性能分析和验证方法平台对算法从架构层次上优化性能。电子系统级设计方法学(Electronic System Level ,ESL)的出现将彻底解决上述问题。
本文将先进的电子系统级设计方法学引入H.264&AVS视频解码SoC系统的设计中。通过ESL性能分析平台分析解码器系统的算法瓶颈,从而对整个系统的任务进行软硬件划分。在此基础上,采用周期精确的SystemC事务级建模对H.264&AVS帧内预测算法与IDCT变换进行建模,把解码加速模块的设计核心放在数据通路的设计上,并将其以并行的方式进行系统集成。
最终建立起基于ESL的软件算法与硬件架构协同仿真验证的SoC协同验证平台,实践证明利用ESL进行系统设计不仅可以有效提高仿真验证速度,而且设计的视频解码硬件能有效改善系统的性能。
With the appearance of 90nm technology, large scale integrated circuit develops rapidly and circuit system becomes more and more complex. The workload of embedded software development and system architecture design is far heavier than the workload to increase the complexity of hardware. Dividing software & hardware at system level at the preliminary stage and developing software in advance decide on the success of a SoC chip. At present, the design of software & hardware co-simulation at RTL level is done at the mid-late stage of the whole design cycle, which is unfavorable to find out the design bottleneck at early time and to develop the software in advance. Advanced video decoding SoC system need dividing software & hardware at OS level at preliminary design stage. Meanwhile, performance optimization of arithmetic at architecture level is required to be done at the platform which has efficient techniques of performance analysis and verification. Electronic System Level provides the solution to those mentioned problems.
This paper is intended to introduce Electronic System Level to the design of H.264&AVS video decoding SoC system. On the ESL performance analysis platform, it is going to analyze the arithmetic bottleneck of decoding system and divide the software & hardware with respect to the whole system’s task. After that, cycle-accurate transaction layer model of system C is used for modeling of intra-prediction arithmetic of H.264&AVS and IDCT transfer. The design core of decoding accelerator module is placed over the data path design。
SoC co-verification platform for co-simulation verification is finally established on the basis of software arithmetic and hardware architecture of ESL. Evidences show that using ESL for system design can not only increase simulation verification speed, but also improve system performance with video decoding hardware.
本文将先进的电子系统级设计方法学引入H.264&AVS视频解码SoC系统的设计中。通过ESL性能分析平台分析解码器系统的算法瓶颈,从而对整个系统的任务进行软硬件划分。在此基础上,采用周期精确的SystemC事务级建模对H.264&AVS帧内预测算法与IDCT变换进行建模,把解码加速模块的设计核心放在数据通路的设计上,并将其以并行的方式进行系统集成。
最终建立起基于ESL的软件算法与硬件架构协同仿真验证的SoC协同验证平台,实践证明利用ESL进行系统设计不仅可以有效提高仿真验证速度,而且设计的视频解码硬件能有效改善系统的性能。
With the appearance of 90nm technology, large scale integrated circuit develops rapidly and circuit system becomes more and more complex. The workload of embedded software development and system architecture design is far heavier than the workload to increase the complexity of hardware. Dividing software & hardware at system level at the preliminary stage and developing software in advance decide on the success of a SoC chip. At present, the design of software & hardware co-simulation at RTL level is done at the mid-late stage of the whole design cycle, which is unfavorable to find out the design bottleneck at early time and to develop the software in advance. Advanced video decoding SoC system need dividing software & hardware at OS level at preliminary design stage. Meanwhile, performance optimization of arithmetic at architecture level is required to be done at the platform which has efficient techniques of performance analysis and verification. Electronic System Level provides the solution to those mentioned problems.
This paper is intended to introduce Electronic System Level to the design of H.264&AVS video decoding SoC system. On the ESL performance analysis platform, it is going to analyze the arithmetic bottleneck of decoding system and divide the software & hardware with respect to the whole system’s task. After that, cycle-accurate transaction layer model of system C is used for modeling of intra-prediction arithmetic of H.264&AVS and IDCT transfer. The design core of decoding accelerator module is placed over the data path design。
SoC co-verification platform for co-simulation verification is finally established on the basis of software arithmetic and hardware architecture of ESL. Evidences show that using ESL for system design can not only increase simulation verification speed, but also improve system performance with video decoding hardware.
引文
[1] Jurgen Teich,“Are current ESL tools meeting the requirements of advanced embedded systems?“, New York, NY USA: ACM Press, 2006, 166-166.
[2]郭炜,郭筝,谢憬等,SOC设计方法与实现,北京:电子工业出版社,2007, 42-48.
[3]毕厚杰,《新一代视频压缩标准—H.264/AVC》,北京:人民邮电出版社,2005,73-86.
[4]高文,王强,马思伟等,AVS数字视频编解码标准,中兴通讯技术,2006,12(3):6-9.
[5] Shekhar Borkar, Thousand core chips: a technology perspective. Proceedings of the 4th annual conference on Design automation 2007, DAC 2007, pp. 746-749, Jun, 2007.
[6] Bergamaschi, Reibaldo; Benini, Luca; Flautner, Krisztian, Wido; Sangiovanni-Vincentelli, Alberto; Wakabayashi, The State of ESL Design. Design & Test of Compters, 25(6): 510-519.
[7] Vincent Perrier,A look inside electronic system level (ESL) design, EE Times, 2004.03.26.
[8]事务级建模标准将开启ESL设计之门,电子工程专辑,2005年10月08日.
[9]冯鑫,郭炜,基于ESL的MPEG-4解码SoC软硬件协同设计,计算机仿真,2007,24(10):257-260.
[10]陈曦,许宁仪,SystemC片上系统设计,北京:科学出版社,2004,68-105.
[11] Transaction level modeling with SystemC, Frank Ghenassia, Springer.
[12] Gupta, Rajesh; Arvind, Berry, Gerard; Brewer, Forrest, Advanced in ESL Design. Design & Test of Compters, 25(6): 520-526.
[13] Thomas Wiegand,Gary J. Sullivan,et al.“Overview of H. 264 VideoCoding Standard”, IEEE Trans. Circuit Syst. Video Technol, 2003, 13(7): 560-576.
[14] F. Bacchini,G. Smith,A. Hosseini,A. Parikh,HT. Chin,P. Urard,E. Girczyc,and S. Bloch,”Building a common ESL design and verification methodology - is it just a dream?”, IEEE /ACM Design Automation Conf (DAC), 2006: 370-371.
[15] Thomas Wiegand, Gary J. Sullivan, et al. Overview of H. 264 VideoCoding Standard. IEEE Trans. Circuit Syst. Video Technol, 2003, 13(7): 560-576.
[16]钱利国,视频编码芯片的设计与优化——在帧内预测与环内滤波设计中的优化实践,硕士学位论文,浙江大学,2006.
[17] YU-wen Huang,Bing-Yu Hsieh,Tung-Chien Chen,and Liang-Gee Chen, HARDWARE ARCHITECTURE DESIGN FOR H.264/AVC INTRA FRAME CODER,Circuits and Systems, 2004, 2, 23-26.
[18] Lain E. G. Richardson, H.264 and MPEG-4 VIDEO COMPRESSION. WILEY, berdeen, UK: the Robert Gordon University, 2003, 16-18.
[19] Steve Furber,“ARM System-on-chip Architecture”, 75 Arlington Street, Suite 300 Boston, MA USA: Addison-Wesley, 2000, 56-78.
[20]刘昊,基于ESL的AVS视频SoC解码器帧内预测算法研究与设计,硕士学位论文,上海交通大学,2008.
[21]彭聪,多模数字视频解码SoC芯片设计与研究,博士学位论文,中国科学院研究生院(计算机技术研究所),2006.
[22]梁剑宇,AVS标准的帧内预测技术研究,硕士学位论文,中山大学,2004.
[23]王争,刘佩玲,AVS帧内预测算法及其解码器的硬件实现,计算机工程与应用,2006,42(19):80-83.
[24] ARM Ltd. SoC Designer Developer’s Guide, Version 3..3[M], March 6th, 2006.
[25]齐晓斌,基于ESL方法的AVS和H.264通用解码器的软硬件协同设计,硕士毕业论文,上海交通大学,2008.
[26]纪秀花,张彩明,适于图像解压的离散余弦逆变换快速算法,北京,计算机学报,2005,28(12):2079-2088.
[27]管海兵,宣国荣,快速DCT算法的蝶形图,微型电脑应用,1999,15(2):24-26.
[28]唐永亮,离散余弦变换的设计与实现,硕士学位论文,天津大学,2008.
[29]郑纬民,汤志忠,计算机系统结构,北京:清华大学出版社,2001,98-194.
[30] R.K.Gupta, Co-Synthesis of Hardware and Software for Digital Embedded Systems, Boston: Kluwer Academic, 1995, 47-72.
[2]郭炜,郭筝,谢憬等,SOC设计方法与实现,北京:电子工业出版社,2007, 42-48.
[3]毕厚杰,《新一代视频压缩标准—H.264/AVC》,北京:人民邮电出版社,2005,73-86.
[4]高文,王强,马思伟等,AVS数字视频编解码标准,中兴通讯技术,2006,12(3):6-9.
[5] Shekhar Borkar, Thousand core chips: a technology perspective. Proceedings of the 4th annual conference on Design automation 2007, DAC 2007, pp. 746-749, Jun, 2007.
[6] Bergamaschi, Reibaldo; Benini, Luca; Flautner, Krisztian, Wido; Sangiovanni-Vincentelli, Alberto; Wakabayashi, The State of ESL Design. Design & Test of Compters, 25(6): 510-519.
[7] Vincent Perrier,A look inside electronic system level (ESL) design, EE Times, 2004.03.26.
[8]事务级建模标准将开启ESL设计之门,电子工程专辑,2005年10月08日.
[9]冯鑫,郭炜,基于ESL的MPEG-4解码SoC软硬件协同设计,计算机仿真,2007,24(10):257-260.
[10]陈曦,许宁仪,SystemC片上系统设计,北京:科学出版社,2004,68-105.
[11] Transaction level modeling with SystemC, Frank Ghenassia, Springer.
[12] Gupta, Rajesh; Arvind, Berry, Gerard; Brewer, Forrest, Advanced in ESL Design. Design & Test of Compters, 25(6): 520-526.
[13] Thomas Wiegand,Gary J. Sullivan,et al.“Overview of H. 264 VideoCoding Standard”, IEEE Trans. Circuit Syst. Video Technol, 2003, 13(7): 560-576.
[14] F. Bacchini,G. Smith,A. Hosseini,A. Parikh,HT. Chin,P. Urard,E. Girczyc,and S. Bloch,”Building a common ESL design and verification methodology - is it just a dream?”, IEEE /ACM Design Automation Conf (DAC), 2006: 370-371.
[15] Thomas Wiegand, Gary J. Sullivan, et al. Overview of H. 264 VideoCoding Standard. IEEE Trans. Circuit Syst. Video Technol, 2003, 13(7): 560-576.
[16]钱利国,视频编码芯片的设计与优化——在帧内预测与环内滤波设计中的优化实践,硕士学位论文,浙江大学,2006.
[17] YU-wen Huang,Bing-Yu Hsieh,Tung-Chien Chen,and Liang-Gee Chen, HARDWARE ARCHITECTURE DESIGN FOR H.264/AVC INTRA FRAME CODER,Circuits and Systems, 2004, 2, 23-26.
[18] Lain E. G. Richardson, H.264 and MPEG-4 VIDEO COMPRESSION. WILEY, berdeen, UK: the Robert Gordon University, 2003, 16-18.
[19] Steve Furber,“ARM System-on-chip Architecture”, 75 Arlington Street, Suite 300 Boston, MA USA: Addison-Wesley, 2000, 56-78.
[20]刘昊,基于ESL的AVS视频SoC解码器帧内预测算法研究与设计,硕士学位论文,上海交通大学,2008.
[21]彭聪,多模数字视频解码SoC芯片设计与研究,博士学位论文,中国科学院研究生院(计算机技术研究所),2006.
[22]梁剑宇,AVS标准的帧内预测技术研究,硕士学位论文,中山大学,2004.
[23]王争,刘佩玲,AVS帧内预测算法及其解码器的硬件实现,计算机工程与应用,2006,42(19):80-83.
[24] ARM Ltd. SoC Designer Developer’s Guide, Version 3..3[M], March 6th, 2006.
[25]齐晓斌,基于ESL方法的AVS和H.264通用解码器的软硬件协同设计,硕士毕业论文,上海交通大学,2008.
[26]纪秀花,张彩明,适于图像解压的离散余弦逆变换快速算法,北京,计算机学报,2005,28(12):2079-2088.
[27]管海兵,宣国荣,快速DCT算法的蝶形图,微型电脑应用,1999,15(2):24-26.
[28]唐永亮,离散余弦变换的设计与实现,硕士学位论文,天津大学,2008.
[29]郑纬民,汤志忠,计算机系统结构,北京:清华大学出版社,2001,98-194.
[30] R.K.Gupta, Co-Synthesis of Hardware and Software for Digital Embedded Systems, Boston: Kluwer Academic, 1995, 47-72.
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