USB2.0 IP核中通用可编程接口及多总线接口（GPMB）的设计与实现
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摘要
通用可编程接口及多总线接口模块（GPIO & MultiBus，简称GPMB）是USB2.0IP核的主要模块之一。它提供32位可编程接口，用户可以通过USB2.0 IP核中的MCU固件对内部相关寄存器进行配置来使用这32位总线，并可以在内部的多总线通道中切换，以达成USB2.0 IP核对外围接口的控制及数据传输，进而完成设备通过USB2.0接口IP核与主机通信的功能。GPMB内部还包含一个Flash控制器模块，使其可用于外围接口为Flash芯片的应用。
本文主要介绍GPMB的硬件设计方法、设计实现及测试过程。首先简要介绍了与本课题相关的USB2.0协议框架、与FLASH芯片相关内容，以及USB2.0 IP核的整体硬件设计，然后详细讲述GPMB模块的设计和实现方法，并将内部的Flash控制器的实现单独进行描述。最后阐述了GPMB模块的单元测试和系统测试方案及结果。
GPMB模块在设计中用电路图描述，在实现过程中用Verilog HDL语言描述，在单元测试中采用模拟MCU对寄存器读写后观察波形的方式，并借助FLASH模型来辅助测试FLASH控制器，系统测试直接在FPGA演示系统上进行，并采用了实际的MCU及FLASH芯片，与其他模块联合测试。
GPMB模块经过了模块仿真及FPGA级验证，达到了设计之初所预计达到的指标。此GPMB模块对类似的IP核设计的用户接口部分有借鉴意义。
The general purpose I/O and MuiltiBus（GPMB） is one of the main modules in the USB2.0 IP Core. GPMB module provides the 32-bit bus between USB2.0 IP Core and peripheral. The bus is programable.at this rate the user can program the MCU firmware to configure the correlative registers before using the bus. The user can also change the bus channel in the GPMB when the data of different type is to be transfered. In conclusion, GPMB module provides the communication channel between USB2.0 IP Core and peripheral. There is a Flash Controller in the GPMB module, and then the USB2.0 IP Core can be used to develop the device containning Flash.
This thesis consists of the designing 、implementing and testing of a GPMB module. First,it briefly introduces the USB2.0 protocol、Flash memory related knowledges and the whole hardware design of USB2.0 IP core.Then it focuses on the design and implementation of the GPMB module, including the Flash Controller. In the end,it describes the unit test and system test procedure of the GPMB.
GPMB is described by circuit diagram during the design phase, but is implemented by the Verilog HDL. In the unit test phase, the testbench simulates reading or writing registers by the MCU, then we can analyse the output waveform. In virtue of Sumsung's Flash memory model, the Flash controller is tested during the unit test phase.The system test of the GPMB is taken with the demo board.
The GPMB module in USB2.0 IP Core has achieved the goal that we drew at the beginning. It provides preliminary study for the similar IP Core.
本文主要介绍GPMB的硬件设计方法、设计实现及测试过程。首先简要介绍了与本课题相关的USB2.0协议框架、与FLASH芯片相关内容，以及USB2.0 IP核的整体硬件设计，然后详细讲述GPMB模块的设计和实现方法，并将内部的Flash控制器的实现单独进行描述。最后阐述了GPMB模块的单元测试和系统测试方案及结果。
GPMB模块在设计中用电路图描述，在实现过程中用Verilog HDL语言描述，在单元测试中采用模拟MCU对寄存器读写后观察波形的方式，并借助FLASH模型来辅助测试FLASH控制器，系统测试直接在FPGA演示系统上进行，并采用了实际的MCU及FLASH芯片，与其他模块联合测试。
GPMB模块经过了模块仿真及FPGA级验证，达到了设计之初所预计达到的指标。此GPMB模块对类似的IP核设计的用户接口部分有借鉴意义。
The general purpose I/O and MuiltiBus（GPMB） is one of the main modules in the USB2.0 IP Core. GPMB module provides the 32-bit bus between USB2.0 IP Core and peripheral. The bus is programable.at this rate the user can program the MCU firmware to configure the correlative registers before using the bus. The user can also change the bus channel in the GPMB when the data of different type is to be transfered. In conclusion, GPMB module provides the communication channel between USB2.0 IP Core and peripheral. There is a Flash Controller in the GPMB module, and then the USB2.0 IP Core can be used to develop the device containning Flash.
This thesis consists of the designing 、implementing and testing of a GPMB module. First,it briefly introduces the USB2.0 protocol、Flash memory related knowledges and the whole hardware design of USB2.0 IP core.Then it focuses on the design and implementation of the GPMB module, including the Flash Controller. In the end,it describes the unit test and system test procedure of the GPMB.
GPMB is described by circuit diagram during the design phase, but is implemented by the Verilog HDL. In the unit test phase, the testbench simulates reading or writing registers by the MCU, then we can analyse the output waveform. In virtue of Sumsung's Flash memory model, the Flash controller is tested during the unit test phase.The system test of the GPMB is taken with the demo board.
The GPMB module in USB2.0 IP Core has achieved the goal that we drew at the beginning. It provides preliminary study for the similar IP Core.
引文
(1) Universal Serial Bus Specification , Revision 2.0.2000
(2) Universal Serial Bus Specification , Revision 1.1.1998
(3) Damjan Lampret, "GPIO IP Core Specification”.www.opencores.org,2001
(4) Rudolf Usselmann,"USB Function IP Core". www.opencores.org,2001
(5) DesignWare DW8051 MacroCell Databook. Synopsys,2002
(6) EZ-USB FX Technical Reference Manual. Cypress,2002
(7) EZ-USB FX2 Technical Reference Manual. Cypress,2002
(8) USB2.0 Transceiver Macrocell Interface（UTMI）Specification, Version 1.05. Intel,2001
(9) DesignWare DW8051 MacroCell Databook, Synopsys，2002
(10) CY7C68013 EZ-USB(r) FX2TM USB Microcontroller High-Speed USB Peripheral Controller, Cypress, 2002
(11) “K9F5608U0B——ECC Algorithm”, SAMSUNG，2001
(12) “K9F5608U0B——32M×8Bit NAND Flash Memory”, SAMSUNG，2001
(2) Universal Serial Bus Specification , Revision 1.1.1998
(3) Damjan Lampret, "GPIO IP Core Specification”.www.opencores.org,2001
(4) Rudolf Usselmann,"USB Function IP Core". www.opencores.org,2001
(5) DesignWare DW8051 MacroCell Databook. Synopsys,2002
(6) EZ-USB FX Technical Reference Manual. Cypress,2002
(7) EZ-USB FX2 Technical Reference Manual. Cypress,2002
(8) USB2.0 Transceiver Macrocell Interface（UTMI）Specification, Version 1.05. Intel,2001
(9) DesignWare DW8051 MacroCell Databook, Synopsys，2002
(10) CY7C68013 EZ-USB(r) FX2TM USB Microcontroller High-Speed USB Peripheral Controller, Cypress, 2002
(11) “K9F5608U0B——ECC Algorithm”, SAMSUNG，2001
(12) “K9F5608U0B——32M×8Bit NAND Flash Memory”, SAMSUNG，2001