应变硅MOS器件阈值电压模型研究
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摘要
应变硅技术通过在MOSFET器件的沟道中引入应力来提高载流子的迁移率,从而提升器件的性能,而且应变硅技术以体Si CMOS工艺为基础,不需要太过复杂的工艺,因而正在作为一种廉价而高效的技术得到越来越广泛的应用,延续着摩尔定律的发展。
本文修正了应变硅和应变SiGe的材料参数以及能带模型,建立了应变SGOI PMOS器件内电势分布的二维泊松方程,通过代入边界条件求解方程,得到了较为精确的阈值电压模型。然后采用Matlab软件对其仿真分析,证明了该模型的正确性。
为了解决现有应变器件存在的短沟道效应严重、亚阈值斜率增大等问题,本文提出了一种双栅应变硅SOI MOSFET新结构,并设计了一套基于现有CMOS工艺的制造流程。通过求解二维泊松方程,建立了双栅应变硅的阈值电压模型。随后采用Matlab软件对其仿真分析,证明了双栅应变硅器件能很好地抑制短沟道效应,栅长可缩短至25nm。利用建立的阈值电压模型,本文还模拟了器件关键参数(如栅氧化层厚度、应变硅厚度、Ge组分等)对器件性能的影响。根据模拟的结果,对这些参数进行优化,提出了较为合理的器件参数值。
By introducing stress into the channel of MOSFET device, strained-silicon technology improves the carrier's mobility, thus enhances the performances of the device. In addition, based on the process of bulk-Si CMOS, strained-silicon technology needs no complex process, is widely applied as a cheap and efficient technology to continue the development of Moore's Law.
This thesis revises the material parameters and energy band models of strained-silicon and strained-SiGe devices, establishes two-dimensional Poisson's equations of electric potential distribution in strained-SGOI PMOS device. By using boundary conditions to solve these equations, an accurate threshold voltage model is obtained. Then the correctness of this model is proved by simulation and analysis using Matlab software.
In order to solve the problems of strained-device, such as: serious short-channel effects, increase of sub-threshold slope and so on, this thesis presents a novel structure called dual-gate strained-silicon SOI MOSFET, and designs a process which is based on existing CMOS manufacturing process. By solving the two-dimensional Poisson's equations of this device, a threshold voltage model is established. After that, the threshold voltage of this novel structure is simulated using Matlab. The results prove that this dual-gate strained-silicon device can control short-channel effects well and has a minimum gate length of 25nm. With the established threshold voltage model, the effects of changes in key device parameters (such as gate oxide thickness, strained-silicon thickness, composition of Ge, etc.) on device performance are also simulated. According to these simulation results, a set of optimal device parameters are proposed.
本文修正了应变硅和应变SiGe的材料参数以及能带模型,建立了应变SGOI PMOS器件内电势分布的二维泊松方程,通过代入边界条件求解方程,得到了较为精确的阈值电压模型。然后采用Matlab软件对其仿真分析,证明了该模型的正确性。
为了解决现有应变器件存在的短沟道效应严重、亚阈值斜率增大等问题,本文提出了一种双栅应变硅SOI MOSFET新结构,并设计了一套基于现有CMOS工艺的制造流程。通过求解二维泊松方程,建立了双栅应变硅的阈值电压模型。随后采用Matlab软件对其仿真分析,证明了双栅应变硅器件能很好地抑制短沟道效应,栅长可缩短至25nm。利用建立的阈值电压模型,本文还模拟了器件关键参数(如栅氧化层厚度、应变硅厚度、Ge组分等)对器件性能的影响。根据模拟的结果,对这些参数进行优化,提出了较为合理的器件参数值。
By introducing stress into the channel of MOSFET device, strained-silicon technology improves the carrier's mobility, thus enhances the performances of the device. In addition, based on the process of bulk-Si CMOS, strained-silicon technology needs no complex process, is widely applied as a cheap and efficient technology to continue the development of Moore's Law.
This thesis revises the material parameters and energy band models of strained-silicon and strained-SiGe devices, establishes two-dimensional Poisson's equations of electric potential distribution in strained-SGOI PMOS device. By using boundary conditions to solve these equations, an accurate threshold voltage model is obtained. Then the correctness of this model is proved by simulation and analysis using Matlab software.
In order to solve the problems of strained-device, such as: serious short-channel effects, increase of sub-threshold slope and so on, this thesis presents a novel structure called dual-gate strained-silicon SOI MOSFET, and designs a process which is based on existing CMOS manufacturing process. By solving the two-dimensional Poisson's equations of this device, a threshold voltage model is established. After that, the threshold voltage of this novel structure is simulated using Matlab. The results prove that this dual-gate strained-silicon device can control short-channel effects well and has a minimum gate length of 25nm. With the established threshold voltage model, the effects of changes in key device parameters (such as gate oxide thickness, strained-silicon thickness, composition of Ge, etc.) on device performance are also simulated. According to these simulation results, a set of optimal device parameters are proposed.
引文
[1] Ma Xiaobo, Liu Weili, Liu Xuyan, et al. Strain stability and carrier mobility enhancement in strained Si on relaxed SiGe-on-insulator. Journal of the Electrochemical Society, 2009, Vol. 157(1), pp.104-108.
[2] Balestra F., New semiconductor devices. Acta Physica Polonica A, 2008. Vol. 114(5), pp. 945-974.
[3] Minjoo L. Lee , Engene A. Fitzgerald. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors. Journal of Applied Physics. 2005. Vol. 97. pp. 1-27.
[4] Olsen S.H., Yan L., Agaiby R., et al. High Strained Si/SiGe MOS technology: Improving gate dielectric integrity. Microelectronic Engineering, 2009, Vol. 86(3), pp. 218-223.
[5] Sverdlov V., Selberherr S., et al. Mobility modeling in advanced MOSFETs with ultra-thin silicon body under stress. ECS Transactions Microelectronics Technology and Devices, 2008, Vol. 14(1), pp.159-168.
[6] Aberg I., Chleirigh C. N., Hoyt J. L., et al. Ultrathin-body strained-Si and SiGe hetero-structure on insulator MOSFETs. IEEE Trans. Electron Devices, 2006, Vol. 53(5), pp. 1021-1029.
[7] Maiti T. K., Das T., Das P. S., et al. Strained-Si MOSFETs for low-power applications. ECS Transactions-Microelectronics Technology and Devices, 2008, Vol. 14(1), pp. 203-211.
[8] Gu W. Y., Liang R. R., Zhang K., Xu J.. Impact of〈100〉Channel Direction for High Mobility p-MOSFETs on Biaxial Strained Silicon. Joural of Semiconductors. 2008, Vol. 29, pp. 1893-1899.
[9] Y. Sun, S. E. Thompson,T. Nishida. Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors. Journal of Applied Physics. 2007, Vol. 101(10), pp. 104503-104503(22).
[10]徐静平,苏邵斌,邹晓。应变SiGe沟道PMOSFET阈值电压模型。固体电子学研究与进展,2008, Vol. 6(28), pp. 180-184.
[11]陈长春,余本海,刘江峰等。提升亚微米Si CMOS器件性能的新技术—应变Si技术。微纳电子技术,2005, Vol. 1, pp. 13-18.
[12] Yen, Wenkuan, Wang Jeanan, Lin Chienting, et al. The impact of stain technology on FUSI gate SOI CMOSFET and device performance enhancement for 45nm nodeand beyond. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, 2008, pp 130-133.
[13] Vinet M., Poiroux T., Widiez J., et al. Bonded planar double metal gate nMOS transistors down to 10nm. IEEE Electron Device Lett., 2005,Vol. 26(5), pp. 317-322.
[14] Kern. Rim, R. Anderson, D. Boyd, et al. Strained Si CMOS (SS CMOS) technology: opportunities and challenges. Solid-State Electronics. Jul. 2003, Vol. 47. pp. 1133-1139.
[15] Soline Richard, Nicolas Cavassilas. Strained silicon on SiGe: Temperature dependance of carrier effective masses. Journal of Applied Physics. Oct. 2003, Vol. 94(8). pp. 5088-5094.
[16] Sverdlov V, Karlowatz G., Dhar S et al. Two-band k .p model for the conduction band in silicon: Impact of strain and confinement on band structure and mobility. Solid-State Electronics, 2008, Vol. 52, 1563-1566.
[17] Smirnov S, Kosina H. Monte Carlo modeling of the electron mobility in strained Si1-xGex layers on arbitrarily oriented Si1-yGey substrates. Solid-State Electronics. 2004, Vol. 48, pp. 1325-1335.
[18] Watling J R, Yang L, Borici M, et al. The impact of interface roughness scattering and degeneracy in relaxed and strained Si n-channel MOSFETs. Solid-State Electronics, 2004, Vol. 48, pp. 1337-1346.
[19] Kern Rim, Judy L. Hoyt, James F. Gibbons. Fabrication and analysis of deep submicron strained-Si N-MOSFET’s. IEEE Transactions on Electron Devices. 2000, Vol. 47. pp. 1406-1415.
[20] Chattopadhyay S., Driscoll L. D., Kwak S K, et al. Strained Si MOSFETs on relaxed SiGe platforms: performance and challenges. Solid-State Electronics, 2004, Vol. 48, pp. 1407-1416.
[21] Ang K. W., Chui K. J., Bliznetsov V, et al. Thin body silicon-insulator NMOSFET with silicon-carbon source/drain regions for performance enhancement. Tech. Dig. IEEE Int. Elec. Dev. Meet. Washington, USA. 2005, pp. 497-500.
[22] H. S. Yang, R. Malik, M. Horstmann, et al. Dual Stress Liner for High Performance sub-45nm Gate Length SO1 CMOS Manufacturing. IEDM 2004, pp. 1075-1077.
[23] Hao Chen, T. L. Lee, T. H. Hou, et al. Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application. IEEE Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 56-57.
[24]周华杰,徐秋霞。应变硅技术。第十四届全国半导体集成电路硅材料学术会议,2005年11月,52-56.
[25] Ji Song Lim, Soctt E. Thompson, Jerry G. Fossum. Comparison of Threshold-Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-MOSFETs. IEEE Electron Device Letters, 2004, Vol. 25(11), pp.731-733.
[26] Jung, Jongwan. Hole mobility and device characteristics of SiGe dual channel structure, Current Applied Physics, 2009, Vol. 9(1), pp. 47-50.
[27] X. Zou, C.X. Li, P. T. Lai, et al. Threshold Voltage Model of SiGe Channel pMOSFET without Si Cap Layer. IEEE Transactions on electron devices, 2005, Vol. 45, pp.123-126.
[28] Vivek Venkataraman, Susheel Nawal, M. Jagadesh Kumar. Compact Analytical Threshold Voltage Model of Nanoscale Fully Depleted Strained Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs. IEEE Translations on Electron Devices, Mar. 2007, Vol. 54(3), pp. 554-562.
[29] Shim Tae-Hun, Kim Seong-Je, Lee Gon-Sub, et al. Hole mobility behavior in strained SiGe-on-SOI p-MOSFETs. Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. ECS Transactions, 2008, Vol. 13(1), pp 345-350.
[30] Takehiro Shinobu, Sakuraba Masao, Murota Junichi, et al. H-performance pMOSFETs with high Ge fraction strained SiGe-heterostructure channel and ultra-shallow source/drain formed by selective B-doped SiGe CVD. Electrical Engineering in Japan, 2008, Vol. 165(3), pp 46-50.
[31] M. Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal. A Simple Analytical Threshold Voltage Model of Nanoscale Single Layer Fully Depleted Strained Silicon on Insulator. IEEE Transactions on electron devices, 2006, Vol. 53, pp.2500-2505.
[32] W. Zhang and J. G. Fossum, On the threshold voltage of strained-Si Si1?xGex MOSFETs. IEEE Trans. Electron Devices, Feb. 2005, Vol. 52(2), pp. 263-268.
[33] Mizuno T., Sugiyama N., Tezuka T., et al. High-performance strained SOI CMOS devices using thin film SiGe-on-insulator technology. IEEE Trans Electron Devices, 2003, Vol. 50(4), pp. 988-992.
[34] Takagi Shinichi. Understanding and engineering of carrier transport in advanced MOS channels. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2008, pp. 9-12.
[35] Grubbs Melody E., Deal Michael, Nishi Yoshio, et al. The effect of oxygen on thework function of tungsten gate electrodes in MOS devices. IEEE Electron Device Letters, 2009, Vol. 30(9), pp. 925-927.
[36] Lin Chia Nan, Yang Yi-Lin Chen Wei Ting, et al. Effect of strain-temperature stress on MOS structure with ultra-thin gate oxide. Microelectronic Engineering, 2008, Vol. 85(9), pp. 1915-1919.
[37] Batwani, Himanshu. Gaur, Mayank. Kumar M. Jagadesh. Analytical drain current model for nano-scale strained-Si/SiGe MOSFETs. COMPEL (The International Journal for Computation and Mathematics in Electrical and Electronic Engineering), 2009, Vol. 28(2), pp. 353-371.
[38] Yeh, Lingyen, Liao, Ming Han, Chen Chun Heng, et al. The dependence of the performance of strained NMOSFETs on channel width. IEEE Transactions on Electron Devices, 2009. Vol. 56(11), pp. 2848-2852,
[39] Hara Y, Takaqi T, Inoue A, et al. Parasitic channels in SiGe heterojunction p-metal oxide semiconductor field effect transistors. Electrochem. Soc, 2002, Vol. 149(7), pp.394-398.
[40] Sareen A., Wang Y, Sodervall U. Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures. J. Appl Phys, 2003, Vol. 93(6), pp. 3545-3551.
[41] Rochette, F., Garros X., Reimbold G..et al. Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset. Microelectronic Engineering, 2009, Vol. 86(7-9), pp. 1897-1900.
[42] Fortunato G., Valletta A., Gaucci L., et al. Short channel effects in poly-silicon thin film transistors. Thin Solid Films, 2005, Vol. 487(1), pp. 221-227.
[43] Khakifirooz Ali, Nayfeh Osama M., Antoniadis Dimitri, et al. A simple semi-empirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters. IEEE Transactions on Electron Devices, 2009, Vol. 56(8), pp. 1674-1680.
[44] Kaushik Roy, Hamid Mahmoodi. Double-Gate SOI Devices for Low-Power and High Performance Applications. IEEE Proceedings of the19th International Conference on VLSI Design(VLSID), 2006, pp.1063-9667.
[45] Ade Ortiz-Conde, Franeiseo J., Garcia-Sanchez, Juan Muci, et al. A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs. IEEE Transaction on Electron Devices, 2007, Vol. 54(1), pp.131-140.
[46] Sun Liwei, Gao Yong, Yang Yuan. Transient characteristic analysis of a double-gatedual-strained-channel SOI CMOS. Chinese Journal of Semiconductors, 2008, Vol. 29(8), pp. 1566-1569.
[47] Ohata Akiko, Gallon Claire, Fenouillet Beranger Claire, et al. Investigation of mobility enhancement effect in process-induced strained ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors. Japanese Journal of Applied Physics, 2008, Vol. 47(4). pp. 2124-2126.
[48] Bera L K, Mukherjee Roy M, Abidha B, et al. A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator. IEEE Electron Device Letter, 2006, Vol. 27(5), pp. 350-355.
[49] Peterson R. L., Sturm J. C.. Dynamics of Uniform Si/SiGe Uniaxial Strain Generation on Compliant Insulating Substrates. SiGe Technology and Device Meeting, 2006, Vol. 3, pp.1-2.
[50] Alatise O. M., Kwa S. K., Olsen, S. H., et al. Improved analog performance of strained Si n-MOSFETs on thin SiGe strained relaxed buffers. Solid-State Device Research Conference, 2008, Vol. 38(9). pp. 99-102.
[51] A. Shimizu, K. Hachimine, N. Ohki, et al. Local mechanical-stress control (LMC): A new technique for CMOS performance enhancement. IEDM Tech Dig., 2001, pp. 433-436.
[52] Zhang Shengdong, Han Ruqi, Lin Xinnan, et al. A stacked CMOS technology on SOI substrate. IEEE Electron Device Lett., 2004, Vol. 25(9), pp. 661-669.
[2] Balestra F., New semiconductor devices. Acta Physica Polonica A, 2008. Vol. 114(5), pp. 945-974.
[3] Minjoo L. Lee , Engene A. Fitzgerald. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors. Journal of Applied Physics. 2005. Vol. 97. pp. 1-27.
[4] Olsen S.H., Yan L., Agaiby R., et al. High Strained Si/SiGe MOS technology: Improving gate dielectric integrity. Microelectronic Engineering, 2009, Vol. 86(3), pp. 218-223.
[5] Sverdlov V., Selberherr S., et al. Mobility modeling in advanced MOSFETs with ultra-thin silicon body under stress. ECS Transactions Microelectronics Technology and Devices, 2008, Vol. 14(1), pp.159-168.
[6] Aberg I., Chleirigh C. N., Hoyt J. L., et al. Ultrathin-body strained-Si and SiGe hetero-structure on insulator MOSFETs. IEEE Trans. Electron Devices, 2006, Vol. 53(5), pp. 1021-1029.
[7] Maiti T. K., Das T., Das P. S., et al. Strained-Si MOSFETs for low-power applications. ECS Transactions-Microelectronics Technology and Devices, 2008, Vol. 14(1), pp. 203-211.
[8] Gu W. Y., Liang R. R., Zhang K., Xu J.. Impact of〈100〉Channel Direction for High Mobility p-MOSFETs on Biaxial Strained Silicon. Joural of Semiconductors. 2008, Vol. 29, pp. 1893-1899.
[9] Y. Sun, S. E. Thompson,T. Nishida. Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors. Journal of Applied Physics. 2007, Vol. 101(10), pp. 104503-104503(22).
[10]徐静平,苏邵斌,邹晓。应变SiGe沟道PMOSFET阈值电压模型。固体电子学研究与进展,2008, Vol. 6(28), pp. 180-184.
[11]陈长春,余本海,刘江峰等。提升亚微米Si CMOS器件性能的新技术—应变Si技术。微纳电子技术,2005, Vol. 1, pp. 13-18.
[12] Yen, Wenkuan, Wang Jeanan, Lin Chienting, et al. The impact of stain technology on FUSI gate SOI CMOSFET and device performance enhancement for 45nm nodeand beyond. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, 2008, pp 130-133.
[13] Vinet M., Poiroux T., Widiez J., et al. Bonded planar double metal gate nMOS transistors down to 10nm. IEEE Electron Device Lett., 2005,Vol. 26(5), pp. 317-322.
[14] Kern. Rim, R. Anderson, D. Boyd, et al. Strained Si CMOS (SS CMOS) technology: opportunities and challenges. Solid-State Electronics. Jul. 2003, Vol. 47. pp. 1133-1139.
[15] Soline Richard, Nicolas Cavassilas. Strained silicon on SiGe: Temperature dependance of carrier effective masses. Journal of Applied Physics. Oct. 2003, Vol. 94(8). pp. 5088-5094.
[16] Sverdlov V, Karlowatz G., Dhar S et al. Two-band k .p model for the conduction band in silicon: Impact of strain and confinement on band structure and mobility. Solid-State Electronics, 2008, Vol. 52, 1563-1566.
[17] Smirnov S, Kosina H. Monte Carlo modeling of the electron mobility in strained Si1-xGex layers on arbitrarily oriented Si1-yGey substrates. Solid-State Electronics. 2004, Vol. 48, pp. 1325-1335.
[18] Watling J R, Yang L, Borici M, et al. The impact of interface roughness scattering and degeneracy in relaxed and strained Si n-channel MOSFETs. Solid-State Electronics, 2004, Vol. 48, pp. 1337-1346.
[19] Kern Rim, Judy L. Hoyt, James F. Gibbons. Fabrication and analysis of deep submicron strained-Si N-MOSFET’s. IEEE Transactions on Electron Devices. 2000, Vol. 47. pp. 1406-1415.
[20] Chattopadhyay S., Driscoll L. D., Kwak S K, et al. Strained Si MOSFETs on relaxed SiGe platforms: performance and challenges. Solid-State Electronics, 2004, Vol. 48, pp. 1407-1416.
[21] Ang K. W., Chui K. J., Bliznetsov V, et al. Thin body silicon-insulator NMOSFET with silicon-carbon source/drain regions for performance enhancement. Tech. Dig. IEEE Int. Elec. Dev. Meet. Washington, USA. 2005, pp. 497-500.
[22] H. S. Yang, R. Malik, M. Horstmann, et al. Dual Stress Liner for High Performance sub-45nm Gate Length SO1 CMOS Manufacturing. IEDM 2004, pp. 1075-1077.
[23] Hao Chen, T. L. Lee, T. H. Hou, et al. Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application. IEEE Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 56-57.
[24]周华杰,徐秋霞。应变硅技术。第十四届全国半导体集成电路硅材料学术会议,2005年11月,52-56.
[25] Ji Song Lim, Soctt E. Thompson, Jerry G. Fossum. Comparison of Threshold-Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-MOSFETs. IEEE Electron Device Letters, 2004, Vol. 25(11), pp.731-733.
[26] Jung, Jongwan. Hole mobility and device characteristics of SiGe dual channel structure, Current Applied Physics, 2009, Vol. 9(1), pp. 47-50.
[27] X. Zou, C.X. Li, P. T. Lai, et al. Threshold Voltage Model of SiGe Channel pMOSFET without Si Cap Layer. IEEE Transactions on electron devices, 2005, Vol. 45, pp.123-126.
[28] Vivek Venkataraman, Susheel Nawal, M. Jagadesh Kumar. Compact Analytical Threshold Voltage Model of Nanoscale Fully Depleted Strained Si on Silicon–Germanium-on-Insulator (SGOI) MOSFETs. IEEE Translations on Electron Devices, Mar. 2007, Vol. 54(3), pp. 554-562.
[29] Shim Tae-Hun, Kim Seong-Je, Lee Gon-Sub, et al. Hole mobility behavior in strained SiGe-on-SOI p-MOSFETs. Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. ECS Transactions, 2008, Vol. 13(1), pp 345-350.
[30] Takehiro Shinobu, Sakuraba Masao, Murota Junichi, et al. H-performance pMOSFETs with high Ge fraction strained SiGe-heterostructure channel and ultra-shallow source/drain formed by selective B-doped SiGe CVD. Electrical Engineering in Japan, 2008, Vol. 165(3), pp 46-50.
[31] M. Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal. A Simple Analytical Threshold Voltage Model of Nanoscale Single Layer Fully Depleted Strained Silicon on Insulator. IEEE Transactions on electron devices, 2006, Vol. 53, pp.2500-2505.
[32] W. Zhang and J. G. Fossum, On the threshold voltage of strained-Si Si1?xGex MOSFETs. IEEE Trans. Electron Devices, Feb. 2005, Vol. 52(2), pp. 263-268.
[33] Mizuno T., Sugiyama N., Tezuka T., et al. High-performance strained SOI CMOS devices using thin film SiGe-on-insulator technology. IEEE Trans Electron Devices, 2003, Vol. 50(4), pp. 988-992.
[34] Takagi Shinichi. Understanding and engineering of carrier transport in advanced MOS channels. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2008, pp. 9-12.
[35] Grubbs Melody E., Deal Michael, Nishi Yoshio, et al. The effect of oxygen on thework function of tungsten gate electrodes in MOS devices. IEEE Electron Device Letters, 2009, Vol. 30(9), pp. 925-927.
[36] Lin Chia Nan, Yang Yi-Lin Chen Wei Ting, et al. Effect of strain-temperature stress on MOS structure with ultra-thin gate oxide. Microelectronic Engineering, 2008, Vol. 85(9), pp. 1915-1919.
[37] Batwani, Himanshu. Gaur, Mayank. Kumar M. Jagadesh. Analytical drain current model for nano-scale strained-Si/SiGe MOSFETs. COMPEL (The International Journal for Computation and Mathematics in Electrical and Electronic Engineering), 2009, Vol. 28(2), pp. 353-371.
[38] Yeh, Lingyen, Liao, Ming Han, Chen Chun Heng, et al. The dependence of the performance of strained NMOSFETs on channel width. IEEE Transactions on Electron Devices, 2009. Vol. 56(11), pp. 2848-2852,
[39] Hara Y, Takaqi T, Inoue A, et al. Parasitic channels in SiGe heterojunction p-metal oxide semiconductor field effect transistors. Electrochem. Soc, 2002, Vol. 149(7), pp.394-398.
[40] Sareen A., Wang Y, Sodervall U. Effect of Si cap layer on parasitic channel operation in Si/SiGe metal-oxide-semiconductor structures. J. Appl Phys, 2003, Vol. 93(6), pp. 3545-3551.
[41] Rochette, F., Garros X., Reimbold G..et al. Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset. Microelectronic Engineering, 2009, Vol. 86(7-9), pp. 1897-1900.
[42] Fortunato G., Valletta A., Gaucci L., et al. Short channel effects in poly-silicon thin film transistors. Thin Solid Films, 2005, Vol. 487(1), pp. 221-227.
[43] Khakifirooz Ali, Nayfeh Osama M., Antoniadis Dimitri, et al. A simple semi-empirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters. IEEE Transactions on Electron Devices, 2009, Vol. 56(8), pp. 1674-1680.
[44] Kaushik Roy, Hamid Mahmoodi. Double-Gate SOI Devices for Low-Power and High Performance Applications. IEEE Proceedings of the19th International Conference on VLSI Design(VLSID), 2006, pp.1063-9667.
[45] Ade Ortiz-Conde, Franeiseo J., Garcia-Sanchez, Juan Muci, et al. A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs. IEEE Transaction on Electron Devices, 2007, Vol. 54(1), pp.131-140.
[46] Sun Liwei, Gao Yong, Yang Yuan. Transient characteristic analysis of a double-gatedual-strained-channel SOI CMOS. Chinese Journal of Semiconductors, 2008, Vol. 29(8), pp. 1566-1569.
[47] Ohata Akiko, Gallon Claire, Fenouillet Beranger Claire, et al. Investigation of mobility enhancement effect in process-induced strained ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors. Japanese Journal of Applied Physics, 2008, Vol. 47(4). pp. 2124-2126.
[48] Bera L K, Mukherjee Roy M, Abidha B, et al. A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator. IEEE Electron Device Letter, 2006, Vol. 27(5), pp. 350-355.
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