机载双基地SAR成像算法的FPGA设计与实现
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摘要
双基地合成孔径雷达(简称双基地SAR或Bistatic SAR)是一种新的成像雷达,也是当今SAR技术的一个发展方向,在军用及民用领域都具有良好的应用前景,近年来成为研究的热点。本文则侧重于研究双基地SAR的距离-多普勒(R-D)成像算法的实现。
在双基地SAR系统及成像算法的研究方面,推导了双基地SAR的系统分辨特性及雷达方程,分析了主要系统参数之间的约束关系。针对正侧视机载双基地SAR系统,本文对距离-多普勒算法进行了推广。最后得到点目标的仿真结果。
在成像算法的FPGA实现上,在System Generator环境下对算法进行定点仿真。完成距离-多普勒成像算法的硬件实现,其中包括了FFT快速傅立叶变换、硬件乘法器、Rocket I/O接口设计、DCM数字时钟管理等主要部分。针对硬件实现的特点,对算法的部分运算进行了简化。
为了对算法实现进行验证,设计开发了该算法的硬件测试平台。主要基于ML310评估板上XC2VP30芯片中嵌入的Power PC 405,完成其硬件部分的设计,主要包括了Aurora协议接口、RS-232串行接口、DDR RAM接口以及其它如中断、时钟等部分。
Bistatic Synthetic Aperture Radar (Bistatic SAR) is a new radar system. It becomes an important development trend in SAR technology field and plays a significant role in military as well as civil application in the future. Bistatic SAR is becoming one of the hotspots in radar imaging technology in recent years. This paper attempts to implement the Range-Doppler (R-D) imaging algorithm on bistatic SAR using FPGAs.
As to imaging algorithm, the paper illustrates the features of Bistatic SAR, derives the Radar fomular,and analyzes the restriction relationship among main parameters. As to broadside airborne bistatic SAR,the paper extends the R-D to conclude the simulation results.
As to the FPGA realization of imaging algorithm, the paper accomplishes fix-point simulation using System Generator, complete FPGA implementation including FFT、multiplier、Rocket I/O、DCM, etc. It simplifies the algorithm in accordance with hardware feature.
To testify this design,the paper developed the hardware testing platform mainly base on ML310 demo board, inchulding one XC2VP30 chip, which has Power PC405 embedded in. The testing board design mainly includes Aurora interface、RS-232、DDR RAM, interrupter and clock, etc..
在双基地SAR系统及成像算法的研究方面,推导了双基地SAR的系统分辨特性及雷达方程,分析了主要系统参数之间的约束关系。针对正侧视机载双基地SAR系统,本文对距离-多普勒算法进行了推广。最后得到点目标的仿真结果。
在成像算法的FPGA实现上,在System Generator环境下对算法进行定点仿真。完成距离-多普勒成像算法的硬件实现,其中包括了FFT快速傅立叶变换、硬件乘法器、Rocket I/O接口设计、DCM数字时钟管理等主要部分。针对硬件实现的特点,对算法的部分运算进行了简化。
为了对算法实现进行验证,设计开发了该算法的硬件测试平台。主要基于ML310评估板上XC2VP30芯片中嵌入的Power PC 405,完成其硬件部分的设计,主要包括了Aurora协议接口、RS-232串行接口、DDR RAM接口以及其它如中断、时钟等部分。
Bistatic Synthetic Aperture Radar (Bistatic SAR) is a new radar system. It becomes an important development trend in SAR technology field and plays a significant role in military as well as civil application in the future. Bistatic SAR is becoming one of the hotspots in radar imaging technology in recent years. This paper attempts to implement the Range-Doppler (R-D) imaging algorithm on bistatic SAR using FPGAs.
As to imaging algorithm, the paper illustrates the features of Bistatic SAR, derives the Radar fomular,and analyzes the restriction relationship among main parameters. As to broadside airborne bistatic SAR,the paper extends the R-D to conclude the simulation results.
As to the FPGA realization of imaging algorithm, the paper accomplishes fix-point simulation using System Generator, complete FPGA implementation including FFT、multiplier、Rocket I/O、DCM, etc. It simplifies the algorithm in accordance with hardware feature.
To testify this design,the paper developed the hardware testing platform mainly base on ML310 demo board, inchulding one XC2VP30 chip, which has Power PC405 embedded in. The testing board design mainly includes Aurora interface、RS-232、DDR RAM, interrupter and clock, etc..
引文
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[2] Willis N J. Bistatic Radar. Technology Service Corporation, Silver Spring, MD, 1995
[3] 汤子跃等,双站 SAR 系统原理.北京: 科学出版社,2003
[4] Horne,et al. Bistatic Synthetic Aperture Radar,Proceedings of Radar 2002 Conference,2002,IEEEpublicationNo.490,pp:6-10
[5] Otmar Loffeld,et al. Models and Useful Relations for Bistatic SAR Processing, IEEE, Vol42, NO.10, OCTOBER 2004 2031
[6] 杨振起.双(多)基地雷达系统,北京: 国防工业出版社,2004
[7] 张澄波.综合孔径雷达原理、系统分析与应用. 北京:科学出版社,1989
[8] H. Cantalloube, et al. Challenges in SAR processing for airborne bistatic acquisitions,5th European Conference on Synthetic Aperture radar,2004
[9] 刘永坦,雷达成像技术.哈尔滨工业大学出版社,1999
[10] I. Walterscheid,et al.Results on bistatic synthetic aperture radar , ELECTRONICS LETTERS 16th September 2004 Vol. 40 No. 19
[11] Roger F,et al. Impact of Ambiguities in Multistatic SAR, Geoscience and Remote Sensing Symposium, IGARSS '04. 2004
[12] Soumekh M. Synthetic Aperture Radar Signal Processing with Matlab Algorithms. John Wiley & Sons, Inc, New York, 1999
[13] Matthias Wei. Synchronisation of Bistatic Radar Systems, Geoscience and Remote Sensing Symposium, IGARSS '04. 2004
[14] Xilinx, Inc. Virtex-II Pro and Virtex-II Pro X FPGA User Guide, V3.0, 2004
[15] Xilinx, Inc.. ML310 User Guide(Virtex-II Pro Embedded Development Platform), V1.1.3, 2004
[16] 张璐. 条带测绘机载双基地 SAR 仿真研究:[硕士学位论文]. 电子科技大学, 2006
[17] 王诚, 薛小刚, 钟信潮. FPGA/CPLD 设计工具 Xilinx ISE 使用详解. 人民邮电出版社, 2005
[18] 夏宇闻.Verilog 数字系统设计教程.北京:北京航空航天大学出版社,2003
[19] Samir Palnitkar. Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition, Publishing House of Electronics Industry, 2004
[20] Xilinx, Inc. Fast Fourier Transform, V3.1, Product Specification, DS260 November 11, 2004
[21] 任艳颖, 王彬. IC 设计基础. 西安电子科技大学出版社, 2003
[22] Xilinx, Inc. RocketIOTM Transceiver User Guide, V2.5, 2004
[23] 任晓东, 文博. CPLD/FPGA 高级应用开发指南. 电子工业出版社, 2003
[24] Xilinx, Inc. FIFO Generator v2.1. Product Specification, DS317, 2005
[25] Xilinx, Inc. PowerPCTM 405 Processor Block Reference Guide, V2.0, 2004
[26] Xilinx, Inc. OPB Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller, Product Specification, DS424, 2004-10
[27] 董代洁, 郭怀理, 曹春雨. 基于 FPGA 的可编程 SoC 设计. 北京航空航天大学出版社,2006
[28] Xilinx, Inc. On-Chip Peripheral Bus V2.0 with OPB Arbiter, Product Specification, DS401, 2004
[29] Xilinx, Inc. Aurora Reference Design User Guide, V2.2, 2004
[30] Xilinx, Inc. OPB Interrupt Controller, Product Specification, DS473, 2004
[31] Xilinx, Inc. EDK OS and Libraries Reference Manual, V4.0, 2005