高性能氮化物半导体MOS-HEMT器件研究
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摘要
论文首先对GaN基MOS-HEMT器件的制作工艺方法进行了研究和优化,在器件表面钝化工艺中,提出了采用先低后高的起辉功率,提高了Si3N4钝化层的薄膜质量;通过调整He和N2的比例,有效地改善了Si3N4钝化层对材料表面所产生的应力和表面粗糙度,明显提高了Si3N4薄膜的击穿电压。通过对Si3N4介质材料进行大量的统计和实验分析,显著提高了生长的均匀性和材料参数的稳定性,使得Si3N4生长厚度偏差小于3%,折射率偏差小于2%,片内均匀性在2%以内。通过优化原子层淀积Al2O3的工艺参数,得到了MOS-HEMT器件所需要的高质量的栅介质;研究并确定了牺牲层的总厚度( >2.5μm)以及牺牲层中PMI胶与电镀层中EMI胶的比例关系和烘烤温度;通过优化空气桥的厚度,电镀速率以及电流密度,确定了最优的电镀方案。最后,通过各步工艺的优化,提出了一种新的高击穿电压和小关态漏电的双场板MOS-HEMT的器件结构。
论文研究了不同凹栅刻蚀深度对MOS-HEMT电容以及器件特性的影响,研究发现经过15s,17s和19s的凹栅刻蚀后,分别形成了1nm,3.2nm和3.7nm的凹栅刻蚀深度,其峰值载流子浓度分别为2.61×1025m-3,2.34×1025m-3和1.79×1025m-3,积分得到的载流子面密度分别为1.12×1017m-2,1.08×1017m-2和1.09×1017m-2。通过变频CV计算,得到了常规MOS-HEMT结构的界面陷阱密度Dit=(0.72 -1.25)×1012cm-2eV-1,界面态时常数τit=(0.64-0.19)μs;而1nm深的凹栅MOS的界面态密度Dit=(0.55-1.08)×1012cm-2eV-1,界面态时常数τit=(0.2-1.59)μs;3.23nm深的凹栅MOS的界面态密度Dit=(0.97-1.14)×1012cm-2eV-1,界面态时常数τit=(0.24-0.49)μs;3.7nm深的凹栅MOS的界面态密度Dit=(0.76 -1.2)×1012cm-2eV-1,界面态时常数τit=(0.19-0.94)μs。可以看出经过凹栅刻蚀后,界面态密度没有增加,反而有小幅的下降,对比界面态时常数的变化,可以看出界面态时常数的量级都在微秒,属于快态陷阱,这说明凹栅结构能够减少Al2O3栅介质与势垒层之间的表面态密度,且不会产生新的界面态陷阱类型。对比研究常规MOS-HEMT器件与凹栅MOS-HEMT器件的直流特性,发现凹栅结构的MOS-HEMT器件在减少Al2O3栅介质与势垒层之间界面态密度的同时,还能够有效地提高器件的饱和输出电流密度;其次,本文发现器件阈值电压从-5.15V增加到-4.4V,跨导峰值随着凹栅深度的增加而增加,从160mS/mm增加到189mS/mm。另外,凹栅结构的MOS-HEMT器件能够有效地去除工艺步骤中低能注入到栅极处的F离子,从而改善因F离子漂移造成的器件电学特性的退化,提高了器件的可靠性。在脉冲测试中,发现常规MOS-HEMT的器件的崩塌最为明显,崩塌量达到20%以上,而凹栅结构的MOS-HEMT器件基本上没有发生明显的崩塌现象。最后研究了凹栅刻蚀对器件功率特性的影响,对几种不同凹栅深度的器件进行了功率测试,发现凹栅型MOS器件能够显著提高器件的功率特性。
论文提出采用O2等离子体处理的方法来减少凹栅刻蚀带来的损伤,由于在O2等离子体处理过程中形成了原位氧化层,因而有效地减小了HEMT电容的频率耗散和高低频CV曲线的漂移,从而使Al2O3/AlGaN之间形成了很高的界面质量。其次,O2等离子体处理后的凹栅型MOS-HEMT保持了较高的饱和输出电流,同时能够有效改善栅极的关态电流和亚阈值特性,脉冲测试的结果表明O2等离子体处理能够消除因凹栅刻蚀所带来的快态陷阱,改善器件的交流特性,随着凹栅刻蚀深度的增加,氧等离子体处理对凹栅型MOS-HEMT器件电学性能的改善更加明显。此外,氧等离子体处理的凹栅型MOS-HEMT器件还具有良好的频率特性。
论文研究并得到了原子层淀积5nm厚Al2O3栅介质的AlGaN/GaN/ Al0.07Ga0.93N(buffer)凹栅型MOS-HEMT器件,缓冲层采用AlGaN的新型凹栅型MOS-HEMT器件的栅长为0.5μm,栅宽为100μm,当栅电压为4V时的最大饱和电流达到894mA/mm;当源漏偏置为10V时,器件的阈值电压为-1.3V,器件的最大跨导达到了223mS/mm。当漏电压从10V变化为30V时,其亚阈值摆幅为650mV/decade,DIBL=42.5mV/V,这说明Al0.07Ga0.93N缓冲层的引入能够很好的抑制漏致势垒降低效应的发生。对于缓冲层采用AlGaN的凹栅型MOS-HEMT器件而言,当漏极电压为160V时,此时的关态电流仅为0.6mA/mm,说明其击穿电压要远大于160V。器件的截止频率达到18GHz以上,其最大振荡频率达到40GHz以上。此外,AlGaN缓冲层结构的凹栅型MOS-HEMT器件还具有良好的功率特性,当漏电压为35V,栅电压接近于截止电压时,器件的饱和功率密度达到7.2W/mm,功率附件效率达到61.4%。对缓冲层采用AlGaN的凹栅型MOS-HEMT器件进行了开态和关态应力的可靠性研究表明,在开态应力下AlGaN/GaN /Al0.07GaN0.93(buffer)凹栅型MOS-HEMT器件的饱和电流,阈值和跨导峰值的退化都比传统GaN缓冲层器件的要小,说明缓冲层采用AlGaN的器件抑制热电子发射效应的作用明显;而在关态应力下AlGaN背势垒结构能够有效地抑制栅极注入电流进入到缓冲层中,因此,对提高器件关态应力下的可靠性也有着积极的作用。
论文研究并得到了原子层淀积5nm厚Al2O3栅介质的高性能AlGaN/AlN/GaN凹栅型MOS-HEMT器件,器件的栅长为0.5μm,栅宽为100μm,器件在栅偏置为-5V完全关断,其关断电流小于0.005mA/mm,具有优良的关断性能;当栅压增加到3V时,凹栅型MOS器件的饱和输出电流密度大于1.6A/mm。AlGaN/AlN/GaN凹栅型MOS-HEMT器件具有极佳的交流特性,脉冲测试表明器件在短脉宽情况下(τ<1μs)发生了很小量的电流崩塌效应,崩塌量小于2.5%,此后随着脉冲宽度的增加,器件基本上没有发生电流崩塌效应。通过电流增益|h21|和功率增益U(MSG/MAG)的外推法,分别得到了器件的截止频率fT=19GHz和最大振荡频率fmax=50GHz,fT和f max的比例为2.6,表明器件具有低的寄生效应。对传统的FET小信号模型进行了优化,考虑到栅极漏电,在原有的本征参数中加入两个反馈电阻Rlgs和Rlgd;考虑到高频下电容的分布特性,再加入Cgsi和Cdsi二个参数来描述pad之间,栅源和漏源之间的交叉影响,在此基础上提出了一种全新的21参数AlGaN/AlN/GaN凹栅MOS-HEMT器件的小信号模型,使模型精度有了很大的提高。此外,新型AlGaN/AlN/GaN凹栅型MOS器件还具有极佳的输出功率和功率附加效率,当测试频率为4GHz,漏压Vd=45V的情况下,器件的最大输出功率密度为13W/mm,功率附加效率更是高达73%以上。当漏电压分别为30V,35V,40V和45V时,AlGaN/AlN/GaN凹栅型MOS-HEMT器件的输出功率密度分别达到6.3W/mm,8.3 W/mm,11.2 W/mm,13 W/mm,其输出功率密度随着漏压的增加呈线性增加的趋势,而其功率附加效率则分别到达72.43%,72.64%,72.74%,73.14%,没有出现退化,保持了极高的功率附加效率,这一结果是目前国内外报道的相关器件特性中最高的。
Firstly, the process of GaN-based MOS-HEMT device is optimized in this paper. The quality of Si3N4 passivation layer is improved by employing elevated plasma power. Stress and roughness of the device surface are improved by adjusting the ratio of He and N2 flow in the passivation process, thus increased the breakdown voltage of the device. Statistical analysis of Si3N4 dielectric material is done through a large number of experiments. The result shows that after optimizing the parameter of the Si3N4 film become stable and the deviation of thickness, the refractive index and the on-chip uniformity are less than 3%, 2% and 2%, respectively. Then, a high-quality gate dielectric is obtained by optimizing the parameter of Al2O3 atomic layer deposition (ALD) process. The total thickness of the sacrificial layer (>2.5μm), the baking temperature and the ratio of PMI and EMI are determined in this paper. By optimizing the thickness of air-bridge, the plating velocity and the current density, we get the optimal plating solution. Finally, a dual field plate MOS-HEMT device with high breakdown voltage and low off-state leakage is developed by optimizing each process step.
The influence of the gate recess etching depth on the characteristics of MOS-HEMT device is investigated in this dissertation, the study found that through the etching time of 15s, 17s and 19s, the recessed gate depth of 1nm, 3.2nm and 3.7nm are formed. The peak carrier concentration are 2.61×1025m-3, 2.34×1025m-3 and 1.79×1025m-3 and the integrated carrier surface density are 1.12×1017m-2, 1.08×1017m-2 and 1.09×1017m-2, respectively. The density and time constant of interface state traps of devices with different gate recess depth are obtained by Gp-ωcalculation. It can be seen that the interface state density does not increase but decrease slightly after etching and the interface state time constant is the order of microseconds, which shows that the recessed gate structure can reduce the interface trap density between Al2O3 dielectric and barrier layer without new type of interface trap generation. Compared with conventional MOS-HEMT devices, the recessed gate MOS-HEMT devices are of better DC performance with higher saturation current density and peak trans-conductance. In addition, the gate recess etching can eliminate the introduction of low-energy F-ions in device process, therefore weakening the degradation of device characteristics caused by F-ion drift and improving the reliability of the device. The current collapse phenomenon is investigated in both conventional MOS-HEMT devices and recessed gate MOS-HEMT devices. A serious current collapse is observed in conventional MOS-HEMT devices, while subtle current collapse is observed in the recessed gate MOS-HEMT devices. Finally, the power characteristic measurement is carried out on conventional MOS-HEMT devices and the recessed gate MOS-HEMT devices, the results suggest that the recessed gate MOS devices are of better power characteristics.
O2 plasma treatment is employed in this paper to reduce the damage caused by gate recess etching. An insitu oxide-layer is formed during the treatment which effectively reduce the frequency dispersion of capacitance and the drift of CV curve, thus forms a very high quality Al2O3/AlGaN interface. Secondly, the O2 plasma treatment can improve DC and AC characteristics of recessed gate MOS-HEMT devices with higher saturated output current, smaller off-state current, better sub-threshold characteristic and less fast-state traps. Finally, the O2 plasma treatment can improve the frequency characteristics of recessed gate MOS-HEMT devices which mainly reflected in the impedance decrease of the output port reflection coefficient (S22).
A high-performance AlGaN/GaN/Al0.07Ga0.93N recessed gate MOS-HEMT device is reported in this paper with a 5nm ALD Al2O3 gate dielectric and an AlGaN buffer layer. The electrical parameters of a device (0.6μm×100μm) are as follows: the threshold voltage is -1.3V, the peak trans-conductance is 223mS/mm and the saturation current is 894mA/mm at Vg=4V. When VD is increased from 10V to 30V, the sub-threshold voltage swing is 650mV/decade and DIBL is 42.5mV/V, which suggests that the introduction of Al0.07Ga0.93N buffer layer can suppress the reduction of barrier height. Recessed gate MOS-HEMT device with AlGaN buffer layer has excellent breakdown performance with the breakdown voltage of above 160V. The fT and fmax of the device are 18GHz and 40G, respectively. Besides, the device also has fairly good power characteristics. The saturation power density and PAE are 7.2W/mm and 61.4%, respectively. On-state and off-state high-electric-field stress results are presented for AlGaN/GaN/Al0.07Ga0.93N (buffer) recessed gate MOS-HEMT devices. Under on-state stress, devices show less DC characteristic degradation than conventional devices, which shows that AlGaN buffer layer can effectively eliminate the hot carrier effects. Under off-state stress, the AlGaN back barrier structure can suppress the injection of gate electrons, thus improving the reliability of the devices. Another high-performance AlGaN/AlN/GaN recessed gate MOS-HEMT device is reported in this paper with a 5nm ALD Al2O3 gate dielectric. The electrical parameters of a device (0.6μm×100μm) are as follows: the pinch off voltage is -5V, the pinch off current is 0.005mA/mm and the saturation current is 1.6A/mm at Vg=3V. This kind of device has excellent AC performance. Minimal current collapse is observed in short pulse-width (τ<1μs) test, while basically no current collapse is observed in long pulse-width test. fT (19GHz) and fmax (50GHz) of devices are obtained by using |H21| and U (MSG/MAG) extrapolation method. The ratio of fT and fmax is 2.6, which show that the device is of low parasitic effect. A 21-parameter small signal model of AlGaN/AlN/GaN recessed gate MOS-HEMT device with higher accuracy is proposed based on the conventional FET small signal model by considering the gate leakage, the distribution character of capacitance under high frequency and the cross impact between Gate-Source and Drain-Source. Besides, this novel AlGaN/AlN/GaN recessed gate MOS-HEMT device is of excellent output power and PAE performance. The maximum output power density and PAE at 4GHz and VD=45V are 13W/mm and 73%. When VD is increased from 30V to 45V, the output power is raised from 6.3W/mm to 13 W/mm linearly, and the PAE is maintained at around 73% without any degradation. It is also believed to be the best microwave performance ever reported in 4GHz for recessed Al2O3/AlGaN/AlN/GaN MOS-HEMTs.
论文研究了不同凹栅刻蚀深度对MOS-HEMT电容以及器件特性的影响,研究发现经过15s,17s和19s的凹栅刻蚀后,分别形成了1nm,3.2nm和3.7nm的凹栅刻蚀深度,其峰值载流子浓度分别为2.61×1025m-3,2.34×1025m-3和1.79×1025m-3,积分得到的载流子面密度分别为1.12×1017m-2,1.08×1017m-2和1.09×1017m-2。通过变频CV计算,得到了常规MOS-HEMT结构的界面陷阱密度Dit=(0.72 -1.25)×1012cm-2eV-1,界面态时常数τit=(0.64-0.19)μs;而1nm深的凹栅MOS的界面态密度Dit=(0.55-1.08)×1012cm-2eV-1,界面态时常数τit=(0.2-1.59)μs;3.23nm深的凹栅MOS的界面态密度Dit=(0.97-1.14)×1012cm-2eV-1,界面态时常数τit=(0.24-0.49)μs;3.7nm深的凹栅MOS的界面态密度Dit=(0.76 -1.2)×1012cm-2eV-1,界面态时常数τit=(0.19-0.94)μs。可以看出经过凹栅刻蚀后,界面态密度没有增加,反而有小幅的下降,对比界面态时常数的变化,可以看出界面态时常数的量级都在微秒,属于快态陷阱,这说明凹栅结构能够减少Al2O3栅介质与势垒层之间的表面态密度,且不会产生新的界面态陷阱类型。对比研究常规MOS-HEMT器件与凹栅MOS-HEMT器件的直流特性,发现凹栅结构的MOS-HEMT器件在减少Al2O3栅介质与势垒层之间界面态密度的同时,还能够有效地提高器件的饱和输出电流密度;其次,本文发现器件阈值电压从-5.15V增加到-4.4V,跨导峰值随着凹栅深度的增加而增加,从160mS/mm增加到189mS/mm。另外,凹栅结构的MOS-HEMT器件能够有效地去除工艺步骤中低能注入到栅极处的F离子,从而改善因F离子漂移造成的器件电学特性的退化,提高了器件的可靠性。在脉冲测试中,发现常规MOS-HEMT的器件的崩塌最为明显,崩塌量达到20%以上,而凹栅结构的MOS-HEMT器件基本上没有发生明显的崩塌现象。最后研究了凹栅刻蚀对器件功率特性的影响,对几种不同凹栅深度的器件进行了功率测试,发现凹栅型MOS器件能够显著提高器件的功率特性。
论文提出采用O2等离子体处理的方法来减少凹栅刻蚀带来的损伤,由于在O2等离子体处理过程中形成了原位氧化层,因而有效地减小了HEMT电容的频率耗散和高低频CV曲线的漂移,从而使Al2O3/AlGaN之间形成了很高的界面质量。其次,O2等离子体处理后的凹栅型MOS-HEMT保持了较高的饱和输出电流,同时能够有效改善栅极的关态电流和亚阈值特性,脉冲测试的结果表明O2等离子体处理能够消除因凹栅刻蚀所带来的快态陷阱,改善器件的交流特性,随着凹栅刻蚀深度的增加,氧等离子体处理对凹栅型MOS-HEMT器件电学性能的改善更加明显。此外,氧等离子体处理的凹栅型MOS-HEMT器件还具有良好的频率特性。
论文研究并得到了原子层淀积5nm厚Al2O3栅介质的AlGaN/GaN/ Al0.07Ga0.93N(buffer)凹栅型MOS-HEMT器件,缓冲层采用AlGaN的新型凹栅型MOS-HEMT器件的栅长为0.5μm,栅宽为100μm,当栅电压为4V时的最大饱和电流达到894mA/mm;当源漏偏置为10V时,器件的阈值电压为-1.3V,器件的最大跨导达到了223mS/mm。当漏电压从10V变化为30V时,其亚阈值摆幅为650mV/decade,DIBL=42.5mV/V,这说明Al0.07Ga0.93N缓冲层的引入能够很好的抑制漏致势垒降低效应的发生。对于缓冲层采用AlGaN的凹栅型MOS-HEMT器件而言,当漏极电压为160V时,此时的关态电流仅为0.6mA/mm,说明其击穿电压要远大于160V。器件的截止频率达到18GHz以上,其最大振荡频率达到40GHz以上。此外,AlGaN缓冲层结构的凹栅型MOS-HEMT器件还具有良好的功率特性,当漏电压为35V,栅电压接近于截止电压时,器件的饱和功率密度达到7.2W/mm,功率附件效率达到61.4%。对缓冲层采用AlGaN的凹栅型MOS-HEMT器件进行了开态和关态应力的可靠性研究表明,在开态应力下AlGaN/GaN /Al0.07GaN0.93(buffer)凹栅型MOS-HEMT器件的饱和电流,阈值和跨导峰值的退化都比传统GaN缓冲层器件的要小,说明缓冲层采用AlGaN的器件抑制热电子发射效应的作用明显;而在关态应力下AlGaN背势垒结构能够有效地抑制栅极注入电流进入到缓冲层中,因此,对提高器件关态应力下的可靠性也有着积极的作用。
论文研究并得到了原子层淀积5nm厚Al2O3栅介质的高性能AlGaN/AlN/GaN凹栅型MOS-HEMT器件,器件的栅长为0.5μm,栅宽为100μm,器件在栅偏置为-5V完全关断,其关断电流小于0.005mA/mm,具有优良的关断性能;当栅压增加到3V时,凹栅型MOS器件的饱和输出电流密度大于1.6A/mm。AlGaN/AlN/GaN凹栅型MOS-HEMT器件具有极佳的交流特性,脉冲测试表明器件在短脉宽情况下(τ<1μs)发生了很小量的电流崩塌效应,崩塌量小于2.5%,此后随着脉冲宽度的增加,器件基本上没有发生电流崩塌效应。通过电流增益|h21|和功率增益U(MSG/MAG)的外推法,分别得到了器件的截止频率fT=19GHz和最大振荡频率fmax=50GHz,fT和f max的比例为2.6,表明器件具有低的寄生效应。对传统的FET小信号模型进行了优化,考虑到栅极漏电,在原有的本征参数中加入两个反馈电阻Rlgs和Rlgd;考虑到高频下电容的分布特性,再加入Cgsi和Cdsi二个参数来描述pad之间,栅源和漏源之间的交叉影响,在此基础上提出了一种全新的21参数AlGaN/AlN/GaN凹栅MOS-HEMT器件的小信号模型,使模型精度有了很大的提高。此外,新型AlGaN/AlN/GaN凹栅型MOS器件还具有极佳的输出功率和功率附加效率,当测试频率为4GHz,漏压Vd=45V的情况下,器件的最大输出功率密度为13W/mm,功率附加效率更是高达73%以上。当漏电压分别为30V,35V,40V和45V时,AlGaN/AlN/GaN凹栅型MOS-HEMT器件的输出功率密度分别达到6.3W/mm,8.3 W/mm,11.2 W/mm,13 W/mm,其输出功率密度随着漏压的增加呈线性增加的趋势,而其功率附加效率则分别到达72.43%,72.64%,72.74%,73.14%,没有出现退化,保持了极高的功率附加效率,这一结果是目前国内外报道的相关器件特性中最高的。
Firstly, the process of GaN-based MOS-HEMT device is optimized in this paper. The quality of Si3N4 passivation layer is improved by employing elevated plasma power. Stress and roughness of the device surface are improved by adjusting the ratio of He and N2 flow in the passivation process, thus increased the breakdown voltage of the device. Statistical analysis of Si3N4 dielectric material is done through a large number of experiments. The result shows that after optimizing the parameter of the Si3N4 film become stable and the deviation of thickness, the refractive index and the on-chip uniformity are less than 3%, 2% and 2%, respectively. Then, a high-quality gate dielectric is obtained by optimizing the parameter of Al2O3 atomic layer deposition (ALD) process. The total thickness of the sacrificial layer (>2.5μm), the baking temperature and the ratio of PMI and EMI are determined in this paper. By optimizing the thickness of air-bridge, the plating velocity and the current density, we get the optimal plating solution. Finally, a dual field plate MOS-HEMT device with high breakdown voltage and low off-state leakage is developed by optimizing each process step.
The influence of the gate recess etching depth on the characteristics of MOS-HEMT device is investigated in this dissertation, the study found that through the etching time of 15s, 17s and 19s, the recessed gate depth of 1nm, 3.2nm and 3.7nm are formed. The peak carrier concentration are 2.61×1025m-3, 2.34×1025m-3 and 1.79×1025m-3 and the integrated carrier surface density are 1.12×1017m-2, 1.08×1017m-2 and 1.09×1017m-2, respectively. The density and time constant of interface state traps of devices with different gate recess depth are obtained by Gp-ωcalculation. It can be seen that the interface state density does not increase but decrease slightly after etching and the interface state time constant is the order of microseconds, which shows that the recessed gate structure can reduce the interface trap density between Al2O3 dielectric and barrier layer without new type of interface trap generation. Compared with conventional MOS-HEMT devices, the recessed gate MOS-HEMT devices are of better DC performance with higher saturation current density and peak trans-conductance. In addition, the gate recess etching can eliminate the introduction of low-energy F-ions in device process, therefore weakening the degradation of device characteristics caused by F-ion drift and improving the reliability of the device. The current collapse phenomenon is investigated in both conventional MOS-HEMT devices and recessed gate MOS-HEMT devices. A serious current collapse is observed in conventional MOS-HEMT devices, while subtle current collapse is observed in the recessed gate MOS-HEMT devices. Finally, the power characteristic measurement is carried out on conventional MOS-HEMT devices and the recessed gate MOS-HEMT devices, the results suggest that the recessed gate MOS devices are of better power characteristics.
O2 plasma treatment is employed in this paper to reduce the damage caused by gate recess etching. An insitu oxide-layer is formed during the treatment which effectively reduce the frequency dispersion of capacitance and the drift of CV curve, thus forms a very high quality Al2O3/AlGaN interface. Secondly, the O2 plasma treatment can improve DC and AC characteristics of recessed gate MOS-HEMT devices with higher saturated output current, smaller off-state current, better sub-threshold characteristic and less fast-state traps. Finally, the O2 plasma treatment can improve the frequency characteristics of recessed gate MOS-HEMT devices which mainly reflected in the impedance decrease of the output port reflection coefficient (S22).
A high-performance AlGaN/GaN/Al0.07Ga0.93N recessed gate MOS-HEMT device is reported in this paper with a 5nm ALD Al2O3 gate dielectric and an AlGaN buffer layer. The electrical parameters of a device (0.6μm×100μm) are as follows: the threshold voltage is -1.3V, the peak trans-conductance is 223mS/mm and the saturation current is 894mA/mm at Vg=4V. When VD is increased from 10V to 30V, the sub-threshold voltage swing is 650mV/decade and DIBL is 42.5mV/V, which suggests that the introduction of Al0.07Ga0.93N buffer layer can suppress the reduction of barrier height. Recessed gate MOS-HEMT device with AlGaN buffer layer has excellent breakdown performance with the breakdown voltage of above 160V. The fT and fmax of the device are 18GHz and 40G, respectively. Besides, the device also has fairly good power characteristics. The saturation power density and PAE are 7.2W/mm and 61.4%, respectively. On-state and off-state high-electric-field stress results are presented for AlGaN/GaN/Al0.07Ga0.93N (buffer) recessed gate MOS-HEMT devices. Under on-state stress, devices show less DC characteristic degradation than conventional devices, which shows that AlGaN buffer layer can effectively eliminate the hot carrier effects. Under off-state stress, the AlGaN back barrier structure can suppress the injection of gate electrons, thus improving the reliability of the devices. Another high-performance AlGaN/AlN/GaN recessed gate MOS-HEMT device is reported in this paper with a 5nm ALD Al2O3 gate dielectric. The electrical parameters of a device (0.6μm×100μm) are as follows: the pinch off voltage is -5V, the pinch off current is 0.005mA/mm and the saturation current is 1.6A/mm at Vg=3V. This kind of device has excellent AC performance. Minimal current collapse is observed in short pulse-width (τ<1μs) test, while basically no current collapse is observed in long pulse-width test. fT (19GHz) and fmax (50GHz) of devices are obtained by using |H21| and U (MSG/MAG) extrapolation method. The ratio of fT and fmax is 2.6, which show that the device is of low parasitic effect. A 21-parameter small signal model of AlGaN/AlN/GaN recessed gate MOS-HEMT device with higher accuracy is proposed based on the conventional FET small signal model by considering the gate leakage, the distribution character of capacitance under high frequency and the cross impact between Gate-Source and Drain-Source. Besides, this novel AlGaN/AlN/GaN recessed gate MOS-HEMT device is of excellent output power and PAE performance. The maximum output power density and PAE at 4GHz and VD=45V are 13W/mm and 73%. When VD is increased from 30V to 45V, the output power is raised from 6.3W/mm to 13 W/mm linearly, and the PAE is maintained at around 73% without any degradation. It is also believed to be the best microwave performance ever reported in 4GHz for recessed Al2O3/AlGaN/AlN/GaN MOS-HEMTs.
引文
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