SOI光波导器件及其增透膜的研究
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摘要
由于其特殊的结构,SOI(Silicon-on-insulator)材料具有优良的光学和电学性能,为超大规模集成电路(VLSI:Very Large Scale Integration)和平而波导技术提供了一个共同的平台。SOI光波导制作工艺与成熟的硅基CMOS工艺相兼容,SOI材料不仅可以制备无源和有源光电子器件,而且还可以和MEMS器件集成。SOI材料上的光电器件的单片集成是光电子产业的发展方向。本论文对SOI大截面脊形波导器件及其相关的增透膜进行了研究。
为减少SOI波导端面菲涅耳反射损耗,寻找合适的增透膜,分别采用PECVD方法制备了SiN_xO_y:H薄膜、IBAD方法制备了氮氧化硅薄膜和电子束蒸发的方法制备了HfO_2薄膜。通过椭圆偏振仪、X-ray光电子能谱、分光计等设备,对制备薄膜的光学性能、成分进行了表征。相关的光学试验结果表明这三种薄膜都是适合硅基光器件的良好的单层增透膜。其中,在光通信窗口1550nm处,通过镀厚度为185nm的HfO_2单层薄膜,双面抛光硅片的菲涅耳损耗降至0.022dB。对于SOI脊形波导器件,从工艺的实际实现条件上,PECVD方法制备SiN_xO_y:H薄膜受到设备结构的限制,不适用波导的端面镀膜;IBAD方法制备氮氧化硅薄膜对于抛光后的SOI端面沉积薄膜不受影响,但是对于集成的波导器件,沉积过程受到限制;电子束蒸发的方法制备HfO_2薄膜由于其特殊的沉积方式,只要有特殊的夹具夹持波导器件,使波导端面垂直于蒸发方向,即可获得高度均匀的HfO_2薄膜,对于集成的波导器件依然可行,这是一种方便简易的镀膜方法。
根据SOI脊形波导单模理论,采用电感耦合反应离子刻蚀制备了高垂直度的SOI脊形波导。为了更好的和光纤耦合,摸索了集成光波导器件的制备工艺。通过对V型槽、U型槽阵列和波导集成的研究,进一步优化了集成SOI波导器件的制备工艺。
采用U型槽阵列制备了集成的光波导器件,成功地实现了在集成波导端面的沉积HfO_2增透膜。在此基础上,对于集成的Y分支和T分支器件进行了研究,对于这些基本器件的研究为后续工作的开展打下了一定的基础。对这些集成器件的光学性能
SOI (Silicon-on-insulator) consists of a thin silicon layer on top of an oxide cladding layer carried on a bare silicon wafer. With its silicon core (n=3.45) and its oxide cladding (n=1.45), it has a high vertical refractive index contrast. Also, both silicon and the oxide are transparent at the telecom wavelength of 1.3um and 1.5um. Due to its special structure, SOI material system, which has very good optical and electronic properties, provides a common platform for VLSI (Very Large Scale Integration) and PLC (Planar Lightwave Circuit). Fabrication process of SOI optical waveguide is very compatible with standard CMOS fabrication processes. Passive and active optoelectronic devices can be fabricated on the SOI wafer, and MEMS devices also can be integrated on the SOI wafer. Monolithic integration of optoelectronic devices on the SOI wafer is the main trend for future optoelectronic industry. Our work in this dissertation is focused on the optical waveguide devices and their anti-reflection coatings in SOI materials.For SOI-based optical waveguide devices, the reflectance and transmittance of uncoated waveguiding silicon layer is almost constant about 31% and 55%, respectively. At the air/waveguide or waveguide/coupling fiber interfaces Fresnel reflection occurs. Fresnel reflection loss of the two waveguide endfaces was calculated to be 3.22dB assuming a normally incident beam. A SOI-based waveguide device needs a high-quality anti-reflection coating on both faces of the device to minimize the Fresnel reflection. To find proper anti-reflection coatings, various methods have been explored to deposit high-quality anti-reflection coatings, including SiN_xO_y:H films deposited by plasma enhanced chemical vapor deposition (PEVCVD), silicon oxynitride films prepared by ion beam assisted deposition (IBAD), and HfO_2 films fabricated by electron beam evaporation. The optical properties and components of the films were characterized by spectroscopic ellipsometry, X-ray photoelectron spectroscopy and Perkin-Elmer Lambda
900 spectrophotometer, etc.. The optical experiment results suggested that all the films were very attractive single layer anti-reflection coatings for the SOI-based optoelectronic devices. And for a coated double-side polished silicon wafer, Fresnel losses at the telecom wavelength of 1550nm have been reduced to 0.022dB by depositing HfO2 film (185nm) as single layer anti-reflection coating. For practical fabrication process, it is very difficult to deposit SiNxOy:H films onto the SOI rib waveguide endfaces due to the size of SOI waveguide devices. Silicon oxynitride films can be deposited onto the SOI rib waveguide endfaces after CMP (chemical Mechanical Polishing), but silicon oxynitride films cannot deposited onto the endfaces of the integrated SOI waveguide devices using IBAD. A clamp fixed the SOI rib waveguide, and the waveguide endfaces were perpendicular to the evaporation direction so that HfO2 could be easily deposited onto the integrated SOI waveguide endfaces using electron beam evaporation.Based on the single-mode waveguide theory, SOI rib waveguides were fabricated by inductive coupled plasma reactive ion etching with vertical sidewall. To achieve the integration of self-alignment connection between single mode fiber and rib waveguide in silicon-on-insulator (SOI) wafer, a three-mask lithography process was used. Uniformity V-grooves and U-grooves were etched by wet etching and dry etching, respectively. The experiment results indicated that the three-mask lithography ICPRIE process is easy, cost-effective and acceptable in a mass production environment. And HfO2 films can be deposited onto the endfaces of the integrated waveguide devices through U-groove.Based on these experiments, the monolithic integration of Y-branch and T-branch devices were fabricated in the SOI wafer , respectively. We measured the fiber-waveguide-fiber insertion losses as the ratio between the output and input powers using Agilent 8164A lightwave measurement system. For the symmetric 1><2 Y-branch with branch angle 28 of 0.8°, the fiber-waveguide-fiber loss was measured to be 4.4dB at X=l.55um. And the results at ?i=l .55 \im are 5.0±0.5 dB and 5.2±0.5 dB, respectively, in the two output waveguides of the 1 x2 single-mode T-branch. The split ratio is nearly 52:48.Endface roughness, surface roughness and sidewall roughness result in increasing scattering losses for waveguides. According to scalar scattering theory, Tien's theory and Marcuse's theory, scattering loss induced by the rms (root-mean-square) roughness was
studied systematically. And the scattering loss is proportional to the square of the sidewall rms roughness.A series of atomic force microscope measurements were carried out to demonstrate the rms roughness of SOI rib waveguide etched by ICPRIE method. To smooth the sidewall surface and corner mirror surface, various methods have been explored. In order not to change the waveguide configuration, low-temperature ultra-high vacuum annealing, hydrogen annealing and mixed ICPRIE were used to reduce the rms roughness of the rough surfaces. After such treatments, the ripples of the surfaces disappeared, and the rms roughness could be reduced to approximately 9nm. With slight shape changed, oxidation and wet etching is a great way to reduce roughness. The SOI rib waveguide devices went through a dry oxidation. After the oxidation step, the SiO2 layers with the thickness of lOOnm were removed by by 40wt.% KOH solutions at 70°C. The ripples of the surfaces disappeared, and the rms roughness could be lowed down to approximately 0.5nm. This is to our knowledge the smallest reported rms roughness for a high-index-difference system such as as SOI rib waveguide.
为减少SOI波导端面菲涅耳反射损耗,寻找合适的增透膜,分别采用PECVD方法制备了SiN_xO_y:H薄膜、IBAD方法制备了氮氧化硅薄膜和电子束蒸发的方法制备了HfO_2薄膜。通过椭圆偏振仪、X-ray光电子能谱、分光计等设备,对制备薄膜的光学性能、成分进行了表征。相关的光学试验结果表明这三种薄膜都是适合硅基光器件的良好的单层增透膜。其中,在光通信窗口1550nm处,通过镀厚度为185nm的HfO_2单层薄膜,双面抛光硅片的菲涅耳损耗降至0.022dB。对于SOI脊形波导器件,从工艺的实际实现条件上,PECVD方法制备SiN_xO_y:H薄膜受到设备结构的限制,不适用波导的端面镀膜;IBAD方法制备氮氧化硅薄膜对于抛光后的SOI端面沉积薄膜不受影响,但是对于集成的波导器件,沉积过程受到限制;电子束蒸发的方法制备HfO_2薄膜由于其特殊的沉积方式,只要有特殊的夹具夹持波导器件,使波导端面垂直于蒸发方向,即可获得高度均匀的HfO_2薄膜,对于集成的波导器件依然可行,这是一种方便简易的镀膜方法。
根据SOI脊形波导单模理论,采用电感耦合反应离子刻蚀制备了高垂直度的SOI脊形波导。为了更好的和光纤耦合,摸索了集成光波导器件的制备工艺。通过对V型槽、U型槽阵列和波导集成的研究,进一步优化了集成SOI波导器件的制备工艺。
采用U型槽阵列制备了集成的光波导器件,成功地实现了在集成波导端面的沉积HfO_2增透膜。在此基础上,对于集成的Y分支和T分支器件进行了研究,对于这些基本器件的研究为后续工作的开展打下了一定的基础。对这些集成器件的光学性能
SOI (Silicon-on-insulator) consists of a thin silicon layer on top of an oxide cladding layer carried on a bare silicon wafer. With its silicon core (n=3.45) and its oxide cladding (n=1.45), it has a high vertical refractive index contrast. Also, both silicon and the oxide are transparent at the telecom wavelength of 1.3um and 1.5um. Due to its special structure, SOI material system, which has very good optical and electronic properties, provides a common platform for VLSI (Very Large Scale Integration) and PLC (Planar Lightwave Circuit). Fabrication process of SOI optical waveguide is very compatible with standard CMOS fabrication processes. Passive and active optoelectronic devices can be fabricated on the SOI wafer, and MEMS devices also can be integrated on the SOI wafer. Monolithic integration of optoelectronic devices on the SOI wafer is the main trend for future optoelectronic industry. Our work in this dissertation is focused on the optical waveguide devices and their anti-reflection coatings in SOI materials.For SOI-based optical waveguide devices, the reflectance and transmittance of uncoated waveguiding silicon layer is almost constant about 31% and 55%, respectively. At the air/waveguide or waveguide/coupling fiber interfaces Fresnel reflection occurs. Fresnel reflection loss of the two waveguide endfaces was calculated to be 3.22dB assuming a normally incident beam. A SOI-based waveguide device needs a high-quality anti-reflection coating on both faces of the device to minimize the Fresnel reflection. To find proper anti-reflection coatings, various methods have been explored to deposit high-quality anti-reflection coatings, including SiN_xO_y:H films deposited by plasma enhanced chemical vapor deposition (PEVCVD), silicon oxynitride films prepared by ion beam assisted deposition (IBAD), and HfO_2 films fabricated by electron beam evaporation. The optical properties and components of the films were characterized by spectroscopic ellipsometry, X-ray photoelectron spectroscopy and Perkin-Elmer Lambda
900 spectrophotometer, etc.. The optical experiment results suggested that all the films were very attractive single layer anti-reflection coatings for the SOI-based optoelectronic devices. And for a coated double-side polished silicon wafer, Fresnel losses at the telecom wavelength of 1550nm have been reduced to 0.022dB by depositing HfO2 film (185nm) as single layer anti-reflection coating. For practical fabrication process, it is very difficult to deposit SiNxOy:H films onto the SOI rib waveguide endfaces due to the size of SOI waveguide devices. Silicon oxynitride films can be deposited onto the SOI rib waveguide endfaces after CMP (chemical Mechanical Polishing), but silicon oxynitride films cannot deposited onto the endfaces of the integrated SOI waveguide devices using IBAD. A clamp fixed the SOI rib waveguide, and the waveguide endfaces were perpendicular to the evaporation direction so that HfO2 could be easily deposited onto the integrated SOI waveguide endfaces using electron beam evaporation.Based on the single-mode waveguide theory, SOI rib waveguides were fabricated by inductive coupled plasma reactive ion etching with vertical sidewall. To achieve the integration of self-alignment connection between single mode fiber and rib waveguide in silicon-on-insulator (SOI) wafer, a three-mask lithography process was used. Uniformity V-grooves and U-grooves were etched by wet etching and dry etching, respectively. The experiment results indicated that the three-mask lithography ICPRIE process is easy, cost-effective and acceptable in a mass production environment. And HfO2 films can be deposited onto the endfaces of the integrated waveguide devices through U-groove.Based on these experiments, the monolithic integration of Y-branch and T-branch devices were fabricated in the SOI wafer , respectively. We measured the fiber-waveguide-fiber insertion losses as the ratio between the output and input powers using Agilent 8164A lightwave measurement system. For the symmetric 1><2 Y-branch with branch angle 28 of 0.8°, the fiber-waveguide-fiber loss was measured to be 4.4dB at X=l.55um. And the results at ?i=l .55 \im are 5.0±0.5 dB and 5.2±0.5 dB, respectively, in the two output waveguides of the 1 x2 single-mode T-branch. The split ratio is nearly 52:48.Endface roughness, surface roughness and sidewall roughness result in increasing scattering losses for waveguides. According to scalar scattering theory, Tien's theory and Marcuse's theory, scattering loss induced by the rms (root-mean-square) roughness was
studied systematically. And the scattering loss is proportional to the square of the sidewall rms roughness.A series of atomic force microscope measurements were carried out to demonstrate the rms roughness of SOI rib waveguide etched by ICPRIE method. To smooth the sidewall surface and corner mirror surface, various methods have been explored. In order not to change the waveguide configuration, low-temperature ultra-high vacuum annealing, hydrogen annealing and mixed ICPRIE were used to reduce the rms roughness of the rough surfaces. After such treatments, the ripples of the surfaces disappeared, and the rms roughness could be reduced to approximately 9nm. With slight shape changed, oxidation and wet etching is a great way to reduce roughness. The SOI rib waveguide devices went through a dry oxidation. After the oxidation step, the SiO2 layers with the thickness of lOOnm were removed by by 40wt.% KOH solutions at 70°C. The ripples of the surfaces disappeared, and the rms roughness could be lowed down to approximately 0.5nm. This is to our knowledge the smallest reported rms roughness for a high-index-difference system such as as SOI rib waveguide.
引文
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