深亚微米IC物理设计中的信号完整性研究
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摘要
随着集成电路特征尺寸的不断缩小,深亚微米、超深亚微米时代已经到来。在芯片功能日趋强大的同时信号完整性问题也已成为当前深亚微米集成电路物理设计中的关键问题。
信号完整性是指信号未受到损伤的一种状态,它表示信号质量和信号传输后仍保持正确的功能特性。对信号完整性收敛产生不利影响的主要有三个因素:串扰、直流电压降和电迁移。其中,对于深亚微米IC影响最大的是串扰,由连线间耦合电容引起的串扰噪声会产生大量的时序违规、逻辑错误。另外,直流电压降和电迁移也会引起芯片性能的降低,甚至导致芯片失效。
本文主要研究基于信号完整性的物理设计流程,包括串扰控制流程、直流电压降分析、金属连线电迁移分析。本文通过HSPICE仿真实验分析了影响串扰的诸多因素与串扰噪声之间的关系,找到减少串扰、修复串扰的理论依据。基于上述分析结果,本文阐述了完整的串扰控制流程,包括串扰的预防、PrimeTime SI结合串扰分析的静态时序分析、PrimeTime SI—Astro的串扰修复流程,并通过实验验证了该串扰控制流程的有效性。结合工程中心Garfiled SoC芯片研究项目,在后端物理设计流程中加入该信号完整性控制流程,大量减少了由于信号完整性问题引起的设计违规,在本文的实验中,存在时序违规的路径数量减少了60%以上,并将修复的迭代次数从八次减少到三次,加速了时序收敛。论文在直流电压降及金属连线电迁移分析的基础上改进电源网络的设计、金属连线的布线,最终消除了芯片中存在的较为严重的电压降。
通过论文的研究工作,Garfiled的设计工艺顺利从0.25μm转为0.18μm,同时消除了信号完整性问题带来的不利影响,芯片主频达到100M,完全达到设计目标。
With the constant shrinking of character size, the era of deep submicron (DSM) and ultra deep submicron (UDSM) has come for the IC industry. Along with the ever growing of chip function, signal integrity has now become the key problem and consideration in the physical design of deep submicron IC.
Signal integrality is the status that the signal is not losing. It is a function character that figures the signal is remain correct after the transmission. There are there factors which influencing the Convergence of Signal integrality in the bad hand. They are crosstalk, IR-drop and electro migration. Which influenced most is crosstalk. Crosstalk noise caused by coupling capacitance will result in a grate deal of timing violation and logical error. IR-drop and electro migration can also reduce the chip performance and even make the chip out of work.
This paper made attention to research the physical design flow which is based on Signal integraty problem mostly including crosstalk control flow, IR-drop analysis, and electro migration analysis. After we analyzed the factors which influence the crosstalk and the crosstalk noise themselves interrelations, by the experiment, we give several advices which can control the crosstalk effectively. Based on the result in front, we expatiated that integrated crosstalk control flow should has three parts, they are crosstalk prevention, PrimeTime SI static timing analysis based on crosstalk and the crosstalk fix flow of PrimeTime SI-Astro. We also validated this crosstalk control flow is effective by experiment. Analysis of IR-drop and electro migration will greatly instruct the design of power supply network and the layout of the signal line. Associate with the research item of Garfiled SoC in our engineering center, we found if we affiliate our signal integrity control flow into the physical design flow, the out of line designs caused by the signal integrity problem reduce a great deal. In this experiment, the amount of violative path is been cut down 60%. Reduce the times of the iteration from 8 to 3, may accelerate timing closure. Improving the design of power network and routing based on the analysis of IR-drop and electro migration,can finally eliminate serious IR-drop existing in the chip.
This paper successfully transfers the process from 0.25μm to 0.18μm ,and remove the influenence of the signal integrity.It makes the main frequency arise to 100MHz and meets our goal.
信号完整性是指信号未受到损伤的一种状态,它表示信号质量和信号传输后仍保持正确的功能特性。对信号完整性收敛产生不利影响的主要有三个因素:串扰、直流电压降和电迁移。其中,对于深亚微米IC影响最大的是串扰,由连线间耦合电容引起的串扰噪声会产生大量的时序违规、逻辑错误。另外,直流电压降和电迁移也会引起芯片性能的降低,甚至导致芯片失效。
本文主要研究基于信号完整性的物理设计流程,包括串扰控制流程、直流电压降分析、金属连线电迁移分析。本文通过HSPICE仿真实验分析了影响串扰的诸多因素与串扰噪声之间的关系,找到减少串扰、修复串扰的理论依据。基于上述分析结果,本文阐述了完整的串扰控制流程,包括串扰的预防、PrimeTime SI结合串扰分析的静态时序分析、PrimeTime SI—Astro的串扰修复流程,并通过实验验证了该串扰控制流程的有效性。结合工程中心Garfiled SoC芯片研究项目,在后端物理设计流程中加入该信号完整性控制流程,大量减少了由于信号完整性问题引起的设计违规,在本文的实验中,存在时序违规的路径数量减少了60%以上,并将修复的迭代次数从八次减少到三次,加速了时序收敛。论文在直流电压降及金属连线电迁移分析的基础上改进电源网络的设计、金属连线的布线,最终消除了芯片中存在的较为严重的电压降。
通过论文的研究工作,Garfiled的设计工艺顺利从0.25μm转为0.18μm,同时消除了信号完整性问题带来的不利影响,芯片主频达到100M,完全达到设计目标。
With the constant shrinking of character size, the era of deep submicron (DSM) and ultra deep submicron (UDSM) has come for the IC industry. Along with the ever growing of chip function, signal integrity has now become the key problem and consideration in the physical design of deep submicron IC.
Signal integrality is the status that the signal is not losing. It is a function character that figures the signal is remain correct after the transmission. There are there factors which influencing the Convergence of Signal integrality in the bad hand. They are crosstalk, IR-drop and electro migration. Which influenced most is crosstalk. Crosstalk noise caused by coupling capacitance will result in a grate deal of timing violation and logical error. IR-drop and electro migration can also reduce the chip performance and even make the chip out of work.
This paper made attention to research the physical design flow which is based on Signal integraty problem mostly including crosstalk control flow, IR-drop analysis, and electro migration analysis. After we analyzed the factors which influence the crosstalk and the crosstalk noise themselves interrelations, by the experiment, we give several advices which can control the crosstalk effectively. Based on the result in front, we expatiated that integrated crosstalk control flow should has three parts, they are crosstalk prevention, PrimeTime SI static timing analysis based on crosstalk and the crosstalk fix flow of PrimeTime SI-Astro. We also validated this crosstalk control flow is effective by experiment. Analysis of IR-drop and electro migration will greatly instruct the design of power supply network and the layout of the signal line. Associate with the research item of Garfiled SoC in our engineering center, we found if we affiliate our signal integrity control flow into the physical design flow, the out of line designs caused by the signal integrity problem reduce a great deal. In this experiment, the amount of violative path is been cut down 60%. Reduce the times of the iteration from 8 to 3, may accelerate timing closure. Improving the design of power network and routing based on the analysis of IR-drop and electro migration,can finally eliminate serious IR-drop existing in the chip.
This paper successfully transfers the process from 0.25μm to 0.18μm ,and remove the influenence of the signal integrity.It makes the main frequency arise to 100MHz and meets our goal.
引文
【1】Crosstalk Noise Control in an SoC Physical Design Flow,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 4, APRIL 2004 ,Murat Becer, Ravi Vaidyanathan, Chanhee Oh, and Rajendran Panda
【2】The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 4, APRIL 2001,Fabrice Caignet, Sonia Delmas-Bendhia, and Etienne Sicard
【3】A Case Study of IR-drop in Structrued At-Speed Testing ,ITC INTERNATIONAL TEST CONFERENCE,N.V.Arvind,Pravin Sreeprakash,and Manfred Hachinger
【4】A Coupled Efficient and Systematic Full-Wave Time-Domain Macromodeling and Circuit Simulation Method for Signal Integrity Analysis of High-Speed Interconnects, IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 27, NO. 1, FEBRUARY 2004 Er-Ping Li,En-Xiao Liu,and Le-Wei Li
【5】Accurate Crosstalk Noise Modeling for Early Signal Integrity Analysis,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 5, MAY 2003,Li Ding, David Blaauw, and Pinaki Mazumder
【6】Analysis of IR-drop Scaling with Implications for Deep Submicron P/G Network Designs,Proceedings of the Fourth International Symposium on Quality Electronic Design,Amir H. Ajami1, Kaustav Banerjee, Amit Mehrotra, and Massoud Pedram1
【 7 】 Analytical Models and Algorithms for the Efficient Signal Integrity Verification of Inductance-Effect-Prominent Multicoupled VLSI Circuit Interconnects,IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 4, APRIL 2004 395,Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, and Jongin Shim
【8】Crosstalk Delay Analysis of a 0.13-μm Node Test Chip and Precise Gate-Level Simulation Technology,IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 5, MAY 2003,Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, and Kazuo Yano
【9】Deep-Submicron Issues in High-Performance Design,David Blaauw ,and Kaushik Gala
【10】Interconnection from Design Perspective,Takayasu Sakurai
【11】Static Timing Analysis for Level-Clocked Circuits in the Presence of Crosstalk,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003,Soha Hassoun, Christopher Cromer, and Eduardo Calvillo-Gámez
【12】The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 4, APRIL 2001,FABRICE CAIGNET, SONIA DELMAS-BENDHIA, AND ETIENNE SICARD
【13】Timing Analysis With Crosstalk is a Fixpoint on a Complete Lattice,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003,Hai Zhou
【14】基于超深亚微米IC 设计的信号完整性研究,《现代电子技术》2004 年第12 期总第179 期,王明虎, 林大俊, 杨依忠, 梁 齐
【15】Signal Integrity for 0118μm CMOS Technology,CHINESE JOURNAL OF SEMICONDUCTORS,Sun Jiaxing , Ye Qing , Zhou Yumei and Ye Tianchun
【16】一种基于电流源模型的芯片系统电源分析与验证方法,国外电子测量技术·2004 年第4 期,邬少国
【17】A Practical Approach to the Full-chip Dynamic IR Drop Verification with Synopsys Tools,SNUG San Jose 2004,Wei-Si Jiang ,and Myung Kong
【18】Addressing Crosstalk Delay – Achieving Timing Closure,SNUG San Jose 2004,Colin MacDonald, and Anis Jarrar
【19】CrossTalk Analysis Using PrimeTime SI,SNUG Europe 2002,Arnaud Lebas,and Peggy Yvay
【20】Crosstalk Driven Placement and Routing Flow In 0.18μm Design,SNUG Korea 2004,Heung-Joon Park, Ki-Dug Sung,Seung-Ho Choi, and Wook-Jin Cha
【21】Crosstalk Noise Analysis and Repair Methodology with PrimeTime-SI,SNUG China 2003,Wei Sufen
【22】Delay Noise Analysis & SI Management with Primetime-SI,SNUG San Jose 2003,Ravi Vaidyanathan, Deryi Sheu , Brian Millar
【23】Hierarchical Crosstalk Analysis Using Interface Logic Models in PrimeTime-SI,SNUG Europe 2004,Henrik Bergendal, Jens C. Michelsen ,and Rainer Mann
【24】Identifying, Prototyping and Fixing Crosstalk Induced Timing Violations with PT-SI and PC,SNUG San Jose 2003,Kwamina Ewusie,and Richard Nouri
【25】Library Considerations When Using PrimeTime SI for Static Crosstalk Analysis,SNUG San Jose 2003,Jason McCampbell
【26】Dynamic Power Net Electromigration and Voltage Drop Analysis Using RailMill,SNUG 1998,KSV Gopalarao
【27】Physical Compiler 用户手册
【28】PrimeTime SI 用户手册
【29】Astro-Rail 用户手册
【30】Astor 用户手册
【2】The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 4, APRIL 2001,Fabrice Caignet, Sonia Delmas-Bendhia, and Etienne Sicard
【3】A Case Study of IR-drop in Structrued At-Speed Testing ,ITC INTERNATIONAL TEST CONFERENCE,N.V.Arvind,Pravin Sreeprakash,and Manfred Hachinger
【4】A Coupled Efficient and Systematic Full-Wave Time-Domain Macromodeling and Circuit Simulation Method for Signal Integrity Analysis of High-Speed Interconnects, IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 27, NO. 1, FEBRUARY 2004 Er-Ping Li,En-Xiao Liu,and Le-Wei Li
【5】Accurate Crosstalk Noise Modeling for Early Signal Integrity Analysis,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 5, MAY 2003,Li Ding, David Blaauw, and Pinaki Mazumder
【6】Analysis of IR-drop Scaling with Implications for Deep Submicron P/G Network Designs,Proceedings of the Fourth International Symposium on Quality Electronic Design,Amir H. Ajami1, Kaustav Banerjee, Amit Mehrotra, and Massoud Pedram1
【 7 】 Analytical Models and Algorithms for the Efficient Signal Integrity Verification of Inductance-Effect-Prominent Multicoupled VLSI Circuit Interconnects,IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 4, APRIL 2004 395,Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, and Jongin Shim
【8】Crosstalk Delay Analysis of a 0.13-μm Node Test Chip and Precise Gate-Level Simulation Technology,IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 5, MAY 2003,Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, and Kazuo Yano
【9】Deep-Submicron Issues in High-Performance Design,David Blaauw ,and Kaushik Gala
【10】Interconnection from Design Perspective,Takayasu Sakurai
【11】Static Timing Analysis for Level-Clocked Circuits in the Presence of Crosstalk,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003,Soha Hassoun, Christopher Cromer, and Eduardo Calvillo-Gámez
【12】The Challenge of Signal Integrity in Deep-Submicrometer CMOS Technology,PROCEEDINGS OF THE IEEE, VOL. 89, NO. 4, APRIL 2001,FABRICE CAIGNET, SONIA DELMAS-BENDHIA, AND ETIENNE SICARD
【13】Timing Analysis With Crosstalk is a Fixpoint on a Complete Lattice,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003,Hai Zhou
【14】基于超深亚微米IC 设计的信号完整性研究,《现代电子技术》2004 年第12 期总第179 期,王明虎, 林大俊, 杨依忠, 梁 齐
【15】Signal Integrity for 0118μm CMOS Technology,CHINESE JOURNAL OF SEMICONDUCTORS,Sun Jiaxing , Ye Qing , Zhou Yumei and Ye Tianchun
【16】一种基于电流源模型的芯片系统电源分析与验证方法,国外电子测量技术·2004 年第4 期,邬少国
【17】A Practical Approach to the Full-chip Dynamic IR Drop Verification with Synopsys Tools,SNUG San Jose 2004,Wei-Si Jiang ,and Myung Kong
【18】Addressing Crosstalk Delay – Achieving Timing Closure,SNUG San Jose 2004,Colin MacDonald, and Anis Jarrar
【19】CrossTalk Analysis Using PrimeTime SI,SNUG Europe 2002,Arnaud Lebas,and Peggy Yvay
【20】Crosstalk Driven Placement and Routing Flow In 0.18μm Design,SNUG Korea 2004,Heung-Joon Park, Ki-Dug Sung,Seung-Ho Choi, and Wook-Jin Cha
【21】Crosstalk Noise Analysis and Repair Methodology with PrimeTime-SI,SNUG China 2003,Wei Sufen
【22】Delay Noise Analysis & SI Management with Primetime-SI,SNUG San Jose 2003,Ravi Vaidyanathan, Deryi Sheu , Brian Millar
【23】Hierarchical Crosstalk Analysis Using Interface Logic Models in PrimeTime-SI,SNUG Europe 2004,Henrik Bergendal, Jens C. Michelsen ,and Rainer Mann
【24】Identifying, Prototyping and Fixing Crosstalk Induced Timing Violations with PT-SI and PC,SNUG San Jose 2003,Kwamina Ewusie,and Richard Nouri
【25】Library Considerations When Using PrimeTime SI for Static Crosstalk Analysis,SNUG San Jose 2003,Jason McCampbell
【26】Dynamic Power Net Electromigration and Voltage Drop Analysis Using RailMill,SNUG 1998,KSV Gopalarao
【27】Physical Compiler 用户手册
【28】PrimeTime SI 用户手册
【29】Astro-Rail 用户手册
【30】Astor 用户手册