高性能存储系统研究
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摘要
随着存储系统的访问速度与处理器的运算速度的差距越来越显著,访存性能已成为提高计算机系统性能的瓶颈。如何通过设计高性能存储系统弥补处理器与存储系统性能的差距长期以来是体系结构领域的研究热点。
本文从提高处理器的IPC值和优化处理器的访存延时及带宽的角度出发,结合分析龙芯2号处理器运行SPEC CPU2000测试程序的访存行为特征,对存储系统性能优化技术进行研究,提出了一系列存储系统的性能优化技术并对所提出的优化技术进行性能评测与分析。本文主要的创新点及贡献包括:
1.通过对Cache写失效行为的分析,提出一种新的提高处理器带宽利用率的Cache写失效处理策略——Cache自适应写分配策略。该策略在访存失效队列中收集全修改Cache块,对全修改Cache块采用非写分配策略,并能够自适应地切换为写分配策略。与传统的Cache写失效处理策略相比,Cache自适应写分配策略硬件代价小,避免了不必要的数据传输,降低Cache污染,减少存储管理队列阻塞的频率。结果表明,采用Cache自适应写分配策略,STREAM基准测试程序带宽平均提高62.6%,SPEC CPU2000程序的IPC值平均提高5.9%。
2.通过对栈访问行为的分析,提出一种栈高速缓存方案——快速地址计算的自适应栈高速缓存组织方案。该方案将栈访问从数据高速缓存的访问中分离出来,充分利用栈空间数据访问的特点,提高指令级并行度,减少数据高速缓存污染,降低数据高速缓存失效率,并采用快速地址计算策略,减少栈访问的命中时间。该栈高速缓存在发生栈溢出时,能够自适应地关闭,以避免栈切换对处理器性能的影响。栈高速缓存标志中增加进程标识,进程切换时不需要将数据写到低层存储系统中,适用于多进程环境。SPEC CPU2000程序运行结果表明,采用快速地址计算的自适应栈高速缓存方案,25.8%的访存指令可以并行执行,数据高速缓存失效率平均降低9.4%,IPC值平均提高6.9%。
3.通过对指令Cache和数据Cache失效行为的分析,提出一种预取策略——结合访存失效队列状态的预取策略。该预取策略保持了指令和数据访问的次序,有利于预取流的提取。并将指令流和数据流的预取相分离,避免相互替换。在预取发起时机的选择上,结合访存失效队列的状态,减小对处理器正常访问请求的影响。通过流过滤机制提高预取准确性,降低预取对访存带宽的需求。结果表明,采用结合访存失效队列状态的预取策略,处理器的平均访存延时减少30%,SPEC CPU2000程序的IPC值平均提高8.3%。
4.通过对内存访问地址的空间局部性分析,提出一种内存控制策略——处理器核指导的内存Page模式控制策略。该策略由处理器核指导,自适应地根据程序访存地址的空间局部性特征动态调整Page模式,融合Open Page策略和Close Page策略的优点。处
With the processor-memory performance gap continuing to grow, the performance of memory access becomes the major bottleneck of the performance improvement for modern microprocessors. It becomes a hot spot of research activities to propose new cache and memory control mechanisms and policies in order that processor-memory gap will be decreased.
Based on investigations of memory access behavior, through experimentations of SPEC CPU2000 benchmarks running on Godson-2 processor, several policies that can improve performance of cache and memory system significantly are proposed and evaluated in this dissertation. The proposed techniques can increase memory access bandwidth while decrease access latency so that IPC of the processor is increased. Following contributions are presented in this dissertation.
1.Cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. Cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Comparing with other cache store miss policies, cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases memory queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing cache adaptive write allocate policy. The performance of SPEC CPU2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.
2.Adaptive stack cache with fast address generation policy is proposed by investigating stack access behavior of programs. Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction-level parallelism, reduces data cache pollution, and decreases data cache miss ratio. Stack access latency can be reduced by using fast address generation scheme proposed here. Adaptive stack cache with fast address generation policy can also avoid unnecessary memory traffic. Stack cache can be disabled adaptively, when it is overflow. It can also be applied to multithread scheme by adding thread identifier. Our experiment results indicate that about 25.8% of all memory reference instructions in SPEC CPU2000 benchmarks are executed in parallel by adopting adaptive stack cache with fast address generation. On average 9.4% data cache miss is reduced. The performance is improved significantly. The average IPC speedup is 6.9%.
3.Prefetching policy using miss queue information is proposed by investigating instruction cache misses and data cache misses. The prefetching policy increases the efficiency
本文从提高处理器的IPC值和优化处理器的访存延时及带宽的角度出发,结合分析龙芯2号处理器运行SPEC CPU2000测试程序的访存行为特征,对存储系统性能优化技术进行研究,提出了一系列存储系统的性能优化技术并对所提出的优化技术进行性能评测与分析。本文主要的创新点及贡献包括:
1.通过对Cache写失效行为的分析,提出一种新的提高处理器带宽利用率的Cache写失效处理策略——Cache自适应写分配策略。该策略在访存失效队列中收集全修改Cache块,对全修改Cache块采用非写分配策略,并能够自适应地切换为写分配策略。与传统的Cache写失效处理策略相比,Cache自适应写分配策略硬件代价小,避免了不必要的数据传输,降低Cache污染,减少存储管理队列阻塞的频率。结果表明,采用Cache自适应写分配策略,STREAM基准测试程序带宽平均提高62.6%,SPEC CPU2000程序的IPC值平均提高5.9%。
2.通过对栈访问行为的分析,提出一种栈高速缓存方案——快速地址计算的自适应栈高速缓存组织方案。该方案将栈访问从数据高速缓存的访问中分离出来,充分利用栈空间数据访问的特点,提高指令级并行度,减少数据高速缓存污染,降低数据高速缓存失效率,并采用快速地址计算策略,减少栈访问的命中时间。该栈高速缓存在发生栈溢出时,能够自适应地关闭,以避免栈切换对处理器性能的影响。栈高速缓存标志中增加进程标识,进程切换时不需要将数据写到低层存储系统中,适用于多进程环境。SPEC CPU2000程序运行结果表明,采用快速地址计算的自适应栈高速缓存方案,25.8%的访存指令可以并行执行,数据高速缓存失效率平均降低9.4%,IPC值平均提高6.9%。
3.通过对指令Cache和数据Cache失效行为的分析,提出一种预取策略——结合访存失效队列状态的预取策略。该预取策略保持了指令和数据访问的次序,有利于预取流的提取。并将指令流和数据流的预取相分离,避免相互替换。在预取发起时机的选择上,结合访存失效队列的状态,减小对处理器正常访问请求的影响。通过流过滤机制提高预取准确性,降低预取对访存带宽的需求。结果表明,采用结合访存失效队列状态的预取策略,处理器的平均访存延时减少30%,SPEC CPU2000程序的IPC值平均提高8.3%。
4.通过对内存访问地址的空间局部性分析,提出一种内存控制策略——处理器核指导的内存Page模式控制策略。该策略由处理器核指导,自适应地根据程序访存地址的空间局部性特征动态调整Page模式,融合Open Page策略和Close Page策略的优点。处
With the processor-memory performance gap continuing to grow, the performance of memory access becomes the major bottleneck of the performance improvement for modern microprocessors. It becomes a hot spot of research activities to propose new cache and memory control mechanisms and policies in order that processor-memory gap will be decreased.
Based on investigations of memory access behavior, through experimentations of SPEC CPU2000 benchmarks running on Godson-2 processor, several policies that can improve performance of cache and memory system significantly are proposed and evaluated in this dissertation. The proposed techniques can increase memory access bandwidth while decrease access latency so that IPC of the processor is increased. Following contributions are presented in this dissertation.
1.Cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. Cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Comparing with other cache store miss policies, cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases memory queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing cache adaptive write allocate policy. The performance of SPEC CPU2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.
2.Adaptive stack cache with fast address generation policy is proposed by investigating stack access behavior of programs. Adaptive stack cache with fast address generation policy decouples stack references from other data references, improves instruction-level parallelism, reduces data cache pollution, and decreases data cache miss ratio. Stack access latency can be reduced by using fast address generation scheme proposed here. Adaptive stack cache with fast address generation policy can also avoid unnecessary memory traffic. Stack cache can be disabled adaptively, when it is overflow. It can also be applied to multithread scheme by adding thread identifier. Our experiment results indicate that about 25.8% of all memory reference instructions in SPEC CPU2000 benchmarks are executed in parallel by adopting adaptive stack cache with fast address generation. On average 9.4% data cache miss is reduced. The performance is improved significantly. The average IPC speedup is 6.9%.
3.Prefetching policy using miss queue information is proposed by investigating instruction cache misses and data cache misses. The prefetching policy increases the efficiency
引文
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