基于工艺波动的互连信号完整性分析
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摘要
随着科学技术的飞速发展,超大规模集成电路制造工艺缩小到深亚微米领域,互连的尺寸不断缩小,集成电路信号面临着严重的互连问题,如信号延时、串扰等等。因此在集成电路设计中,互连工艺波动对集成电路性能的影响变得至关重要。为了有效分析工艺波动对互连性能的影响,本文着重研究超大规模集成电路中互连工艺波动对互连延时和串扰噪声的影响。通过分析互连几何参数波动与互连寄生参数的关系,得到其近似的函数关系表达式。基于工艺波动分别建立RC互连延时、RLC互连延时和互连串扰统计模型,并利用本文提出的模型得到互连延时和串扰噪声均值和标准差的解析表达式。与目前广泛应用的蒙特卡罗仿真相比,本文所提方法在确保计算精度的前提下大大缩短了计算时间,仿真表明本文方法具有较高的效率和精度,实用性更强。
With the rapid development of technology, very large scale integrated circuits manufacturing process technologies going into the deep submicron regime, rapidly decreasing minimum feature size bring to the forefront new physical issues such as delay and crosstalk. So the impact of process fluctuations on performance has become extremely critical in IC design. To effectively analyze impact of process fluctuations on interconnect performance, the impact of interconnect process fluctuations on the interconnect delay and crosstalk noise in VLSI is studied and discussed in the thesis. The approximate function relationships are obtained by analyzing the impact of interconnect geometric parameters fluctuation on the interconnect parasitic parameters. The statistical RC interconnect delay model, RLC interconnect delay model and crosstalk noise model are successfully proposed and built respectively. The mathematical expressions of mean and standard deviation of interconnect delay and crosstalk noise can be obtained by using the proposed models. The time of calculation is greatly shortened with a good calculating precision using the obtained method compared with the widely used Monte Carlo simulations. It is proved that they have high efficiency and are accurate enough, so our models are more practical.
With the rapid development of technology, very large scale integrated circuits manufacturing process technologies going into the deep submicron regime, rapidly decreasing minimum feature size bring to the forefront new physical issues such as delay and crosstalk. So the impact of process fluctuations on performance has become extremely critical in IC design. To effectively analyze impact of process fluctuations on interconnect performance, the impact of interconnect process fluctuations on the interconnect delay and crosstalk noise in VLSI is studied and discussed in the thesis. The approximate function relationships are obtained by analyzing the impact of interconnect geometric parameters fluctuation on the interconnect parasitic parameters. The statistical RC interconnect delay model, RLC interconnect delay model and crosstalk noise model are successfully proposed and built respectively. The mathematical expressions of mean and standard deviation of interconnect delay and crosstalk noise can be obtained by using the proposed models. The time of calculation is greatly shortened with a good calculating precision using the obtained method compared with the widely used Monte Carlo simulations. It is proved that they have high efficiency and are accurate enough, so our models are more practical.
引文
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[45]J.Cong. An interconnect-centric design flow for nanometer technologies. In Pro- c.Intl.Symp.VLSI Technology, Systems, and Applications, 1999, 54-57.
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[3]王阳元,康晋峰.深亚微米集成电路中的互连问题—低k介质与Cu的互连集成技术.半导体学报,2002, 23(11): 1121-1134.
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[6] J.Cong. An interconnect-centric design flow for nanometer technologies. Proceed- ings of the IEEE, 2001, 89(4): 505-528.
[7] Banerjee Kaustav, Mehrotra Amit. Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling[J]. IEEE Sy- mposium on VLSI Circuits, 2001, 6: 14-16.
[8] Kanak Agarwal, Dennis Sylvester. Statistical Interconnect Metrics for Physical- Design Optimization[J]. IEEE Transactions on computer-aided design of integrated circuits and systems,2006, 25(7): 1273-1288.
[9] Dai.W, Hao Ji. Timing analysis taking into account interconnect process variation. IEEE International Workshop on Statistical Methodology, 2001, 51-53.
[10]Stine.B.E, D.S.Boning, J.E.Chung. Analysis and decomposition of spatial variation in integrated circuit processes and devices. IEEE Trans.Semiconductor Manufac- turing, 1997, 10(1): 24-41.
[11]Nassif.S.R. Modeling and analysis of manufacturing variations. IEEE Conference on Custom Integrated Circuits, 2001, 223-228.
[12]Sengupta, M.S Saxena, L Daldoss. Application specific worst case corners using response surfaces and statistical models. Digital Object Identifier, 2004, 351-56.
[13]Sylvester.D, O.S.Nakagawa, Chenming Hu. Modeling the impact of back-end process variation on circuit performance. International Symposium on VLSITechnology, Systems and Applications, 1999, 58-61.
[14]Nakagava.O.S, N Chang, S Lin. Circuit impact and skew-corner analysis of sto- chastic process variation in global interconnect, 1999, 230-232.
[15]Nagaraj.N.S, P Balsara, C Cantrell. Crosstalk noise verification in digital designs with interconnect process variations. Fourteenth International Conference on VLSI Design, 2001, 365-370.
[16]Liu Ying, S.R.Nassif, L.T Pileggi. Impact of interconnect variations on the clock skew of a gigahertz microprocessor. 37th Design Automation Conference, 2002, 168-171.
[17]Acar.E, S.Nsssif, Liu Ying. Assessment of true worst case circuit performance under interconnect parameter variations. 2001 International Symposium on Quality Electronic Design,2001,431-436.
[18]Zhang, Lizheng, Chen Weijun. Correlation-preserved non-Gaussian statistical timing analysis with quadratic timing model. 42nd Design Automation Confere- nce,2005,83-88.
[19]Zhan.Y, A.J Strojwas, X Li. Correlation-aware statistical timing analysis with non-Gaussian delay distributions. 42nd Design Automation Conference, 2005, 77-82.
[20]Sauter.S, R Thewes, W Weber. Effect of parameter variations at chip and wafer level on clock skews. IEEE Transactions on Semiconductor Manufacturing, 2000, 13(4): 395-400.
[21]Lin.Z.J, C Spanos, L Milor. Study of circuit sensitivity to interconnect variation. 2nd International Workshop on Statistical Metrology, 1997, 28-31.
[22]Lin.Z.J, C Spanos. Sensitivity study of interconnect variation using statistical experimental design. 3rd International Workshop on Statistical Metrology, 1998, 68-71.
[23]Ahn, Seungyoung, A.C.W Lu. Effects of process variation on signal integrity for high speed differential signaling on package level. 4th Electronics Packaging Tec- hnology Conference, 2002, 249-252.
[24]Zhang Qiang, J McMacken. Development of Robust interconnect model based on design of experiments and multiobjective optimization. IEEE Transactions on Electron Devices, 2001, 48(9): 1885-1891.
[25]Nurmi.T, S Tuuna, J Isoaho. Evaluating the relative effect of process variations and switching patterns on BUS performance towards nano-scale interconnects. International Symposium on Signals, Circuits and Systems, 2005, 59-62.
[26]Nakagawa.O.S, S.Y Oh, G Ray. Modeling of pattern-dependent on-chip intercom- nect geometry variation for deep-submicron process and design technology. International Electron Devices Meeting, 1997, 137-140.
[27]Bhavnagarwala.A.J, A Kapoor, J.D Meindl. Impact of interconnect parameter variations on wire-tree delay. International Workshop on Statistical Metrology,2000, 80-83.
[28]Lu, Xiang, Zhuo Li, et.al. PARADE: PARAmetric delay evaluation under process variation.5th International Symposium on Quality Electronic Design, 2004, 276-280.
[29]Rajaram.A, Lu Bing, Guo Wei, et al. Analytical Bound for unwanted clock skew due to wire width variation. International Conference on Computer Aided Design, 2003, 401-406.
[30]Agarwal.K, D Sylvester, D Blaauw. Variational Delay Metrics for Interconnect Timing Analysis. 41st Design Automation Conference, 2004, 381-384.
[31]Agarwal.K, M Agarwal, D Sylvester, et al. Statistical interconnect metrics for physical design optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(7): 1273-1288.
[32]M Agarwal, Agarwal.K, D Sylvester, et al. Statistical modeling of cross-coupling effects in VLSI interconnects. Asia and South Pacific Design Automation Con- ference, 2005, 503-506.
[33]Kankani.N, V Agarwal, J Wang. A probabilistic analysis of pipelined global interconnect under process variations. Asia and South Pacific Conference on Design Automation, 2006, 724-729.
[34]Narasimba.U, B Abraham, Nagaraj NS. Statistical Analysis of Capacitance Coupl- ing Effects on Delay and Noise. 7th International Symposium on Quality Electronic Design, 2006.
[35]郝跃,荆明娥,马佩军. VLSI集成电路参数成品率及优化研究进展.电子学报,2003, 31(12A): 1971-1974.
[36]马佩军,郝跃.提高成品率的VLSI互连线线宽优化.西安电子科技大学报(自然科学版), 2002, 29(1): 10-14.
[37]蔡懿慈,熊焰,洪先龙.考虑工艺参数变化的安全时钟布线算法.中国科学E辑信息科学, 2005, 35(8): 887-896.
[38]董刚. RLC互连效应的模型及模拟研究.西安电子科技大学博士学位论文,2004.
[39]J.Heidenreich, D.Edelstein, R.Goldblatt, et al. Copper dual damascene for sub 0.25um CMOS. IEEE International Interconnect Technology Conference, 1998,151-153.
[40]B.Zhao, D.Feiler, V.Ramanathan, et al. A Cu/low-k dual damascene interconnect for high performance and low cost integrated circuits. IEEE Symposium on VLSI Technology, 1998, 28-29.
[41]S.M.Chai, A.Gentile, W.E.Lugo-Beauchamp. Focal plane processing architectures for real time hyper spectral image processing. Applied Optics, 2000, 39(5): 835-849.
[42]W.Dally. Interconnect limited VLSI architecture. IEEE International Interconnect Technology Conference, 1999, 15-17.
[43]A.V.Krishnamoorthy, D.A.B.Miller. Scaling optoelectronic VLSI circuits into the 21st century: A technology roadmap. IEEE Journal on Selected Topics in Quantum Electronics, 1996, 2(4): 55-76.
[44]J.W.Joyner, P.Zarkesh-Ha, J.A.Davis, et.al. A three-dimensional stochastic wire- length distribution for variable separation of strata. IEEE International Technology Conference, 2000, 176-179.
[45]J.Cong. An interconnect-centric design flow for nanometer technologies. In Pro- c.Intl.Symp.VLSI Technology, Systems, and Applications, 1999, 54-57.
[46]Flynn M.J, Hung P. Rudd K.W. Deep-Submicron Microprocessor Design Issues. Digital Object Identifier, 1999, 19(4): 11-22.
[47]刘艳红,赵宇,王美田.深亚微米MOS器件的物理、结构与工艺.半导体杂志, 2000, 25(1): 35-39.
[48]J.M.Rabaey, Digital Integrated Circuits, A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996.
[49]Y.I.Ismail, E.G.Friedman, J.L.Neves. Figures of merit to characterize the impo- rtance of on-chip inductance. IEEE/ACM Design Automation Conf, 1998, 560-565.
[50]L.Nagel. Spice, a computer program to simulation semiconductor circuits.Univ.Ca- lifornia,Berkeley,CA,TR ERL-M520, 1995.
[51]The AS/X User’s Guide.IBM Corp, 1996.
[52]L.T.Pillage, R.A.Rohrer. Asymptotic waveform evaluation for timing analysis.IEEE Tran.Computer-Aided Design, 1990, 9(4): 352-366.
[53]Elmore.W.C. The transient response of damped linear networks with particular regard to wide-band amplifiers. Journal of Applied Physics, 1948, 19 (1): 55-63.
[54]A.B.Kahng, S.Muddu. Accurate analytical delay models for VLSI interconnect- ts.Univ.California,Los Angeles,CA,UCLA CS Dept.TR-950034, 1995.
[55]Sylvester.D, Nakagawa.O.S. Modeling the impact of back-end process variation on circuit performance[J]. International Symposium on VLSI Technology, Systems andApplications, 1999: 58-61.
[56]B.Tutuianu, F Dartu, L.Pileggi. Explicit RC-ciruit delay approximation based on the first three moments of the impulse response. in Proc.IEEE Design Automation Conf, 1996, 611-616.
[57]R.Kay, L.Pileggi. PRIMO: probability interpretation of moments for delay calc- ulation. in Proc.IEEE Design Automation Conference, 1998, 463-468.
[58]Tao Lin, Emrah Acar, LPileggi. h-gamma: An RC delay metric based on a gamma distribution approximation to the homogenous response[J]. Proc.Int.Conf.Com- puter-Aided Design,San Jose,CA, 1998, 19–25.
[59]Xiaodong Yang, Walter H.Ku, Chungkuan Cheng. RLC Interconnect delay estim ation via moments of Amplitude and Phase Response. in Proc.IEEE Int.Conf.Co- mputer -Aided Design, 1998, 19-25.
[60]Charles J.Alpert,Frank Liu,Chandramouli Kashyap. Delay and Slew Metrics Usi- ng the Lognormal Distribution[J]. Proc.Design Automation Conf.Anaheim,CA, 2003,24(2):950–953.
[61]Liu F, Kashyap C, Alpert C J. A Delay Metric for RC Circuits Based on the Weibull Distribution. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23(3): 443-447.
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